archive notice

Reviewed-on: amberisvibin/chibi-pc09#1

README.md

@@ -1,17 +1,27 @@
 # chibi pc-09
-![GitHub last commit](https://img.shields.io/github/last-commit/amberisvibin/chibi-pc80)
+
+## Archived!
+
+This repo has been archived, and the different parts have been migrated to other repos.
+
+The PCB for prototype 1 has been moved to https://gitea.ambersplace.net/chibi/pc09-prototype-1
+
+The firmware has been moved to https://gitea.ambersplace.net/chibi/chibi-firmware
+
+![Gitea last commit](https://img.shields.io/gitea/last-commit/amberisvibin/chibi-pc09?gitea_url=https%3A%2F%2Fgitea.ambersplace.net&style=for-the-badge&label=Last%20Gitea%20Commit)
+![GitHub last commit](https://img.shields.io/github/last-commit/amberisvibin/chibi-pc09?style=for-the-badge&label=Last%20Github%20Commit)
 
 ## Description
 
-The PC-09 will be a 6309 based microcomputer with a 74LS612 MMU, uPD72020 graphics, PS/2 keyboard and mouse input, and a capable UART. 
+The PC-09 will be a 6309 based microcomputer with an MMU using 74HC670 register files and dual 16550 UARTs. The plan is to eventually add uPD7220 graphics and PS/2 mouse and keyboard.
 
-The MMU will allow up to 2 megabytes of I/O to be paged into the address space. Pages are 4k. System storage will be paged into the address space as well, as it will be either EEPROM or flash. 
+The two 74HC670s will take the top 4 bits of the address bus and expand them to 8 bits, turning the 16 bit cpu address space into a 20 bit address space capable of addressing 1MB of memory. Memory pages are 4KB. Being a register file, any page can be mapped to any slot, allowing complex memory management schemes.
 
-The uPD72020 is a very advanced graphics chip for it's time, capable of accelerated drawing of lines, shapes, fills, and characters. It can be coerced into outputting a VGA signal at 640x480 and *maybe* 800x600. 
+The 16550 UART is capable of interrupt driven operation with FIFOs, allowing for characters to be processed in batches rather than individually, minimizing task switch delays. They also support hardware flow control, and some versions can automatically assert RTS when the FIFO is nearing full.
 
-Keyboard and mouse will be handled by the VIA VT82C42. It is an Intel 8242 compatible controller capable of both PS/2 keyboard and mouse. It's interface is relatively simple, which makes connection easy. It relies on interrupts, so an interrupt system will be required.
+The uPD7220 graphics are very powerful, allowing 16 colors at 640x480, but it is a complex chip to get working. It will be left for a later date.
 
-To avoid the infamous 65C22 bug, the system will use the 16550 UART from the PC ecosystem. It is *relatively* easy to interface this to a 6800 style bus. It has more features than a 65C22 as well. As configured, it will be stable up to 38,400 baud. 
+The solution for PS/2 keyboard and mouse have not yet been decided.
 
 ## Progress
 
@@ -21,6 +31,8 @@ Prototype 1 is currently in progress. It will be a much simpler system. It will
 
 The PCB and parts for Prototype #1 have been ordered, and assembly will begin soon. Initial test code is now available in the code/ directory.
 
+Assembly is in progress.
+
 ## License
 
-This project is licensed under the MIT license. This applies to both the hardware (schematics, bill of materials, pcb layouts) and documentation. This does *not* apply to the datasheets/ directory, the books/ directory or code/assist09/. Those files belong to their respective copyright holders.
+This project is licensed under the MIT license. This applies to both the hardware (schematics, bill of materials, pcb layouts) and documentation. This does *not* apply to the datasheets/ directory or code/assist09/. Those files belong to their respective copyright holders.

code/boot/README.md

@@ -22,7 +22,7 @@ From there all you should have to do to generate a `boot.bin` is:
 
 ```sh
 git clone https://github.com/amberisvibin/chibi-pc09.git
-cd chibi-pc09
+cd chibi-pc09/code/boot
 make
 ```
 

code/boot/linkscript

@@ -0,0 +1,5 @@
+section RESET load 8000
+section SERIAL
+section MEMTEST
+
+section VECTORS high 100000

code/boot/makefile

@@ -8,26 +8,45 @@
 # Project Defaults & Folders
 # ------------------------------------------------------------------------------
 
-TARGET  := boot.bin
+TARGET  := boot
+TARGROM := $(TARGET).bin
 SRCDIR  := src/
-MAINSRC := $(SRCDIR)boot.s
+BUILDDIR := build/
 SRCS    := $(wildcard $(SRCDIR)*.s)
+OBJS    := $(patsubst $(SRCDIR)%.s,$(BUILDDIR)%.o,$(SRCS))
 INCS    := $(wildcard $(SRCDIR)*.inc)
 
 # ------------------------------------------------------------------------------
 # Toolchain Definitions
 # ------------------------------------------------------------------------------
 
-AS := asm6809
+AS  := lwasm
+LD  := lwlink
+FIX := mot2bin
+
+ASFLAGS := -f obj
+LDFLAGS := -f srec -m map.txt -s linkscript
 
 # ------------------------------------------------------------------------------
 # Rules and Phony Targets
 # ------------------------------------------------------------------------------
 
-all: $(TARGET)
+all: $(TARGROM)
 
-$(TARGET): $(SRCS) $(INCS)
-	$(AS) -o $(TARGET) $(MAINSRC)
+# Fix srec into flashable bin file
+$(TARGROM): $(TARGET).s19
+	$(FIX) -out $@ $<
 
+# Link objects
+$(TARGET).s19: $(OBJS)
+	$(LD) $(LDFLAGS) -o $@ $^
+
+# Assemble objects
+$(OBJS): $(BUILDDIR)%.o : $(SRCDIR)%.s
+	-@mkdir -p $(BUILDDIR)
+	$(AS) $(ASFLAGS) -o $@ $<
+
+.IGNORE: clean
 clean:
-	rm -v $(TARGET)
+	@echo 'Cleaning up intermediary files...'
+	@rm -rv $(TARGROM) $(TARGET).s19 map.txt $(BUILDDIR)

code/boot/src/boot.s

@@ -1,54 +0,0 @@
-; CHIBI PC-09 Prototype #1 Boot ROM -- Hardware Initialization and Reset Vecs
-; Copyright (c) 2024 Amber Zeller, Gale Faraday
-; Licensed under MIT
-
-  INCLUDE "src/hardware.inc"
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Hardware Initialization Routines
-;;
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-  ORG ROM_BASE
-
-RESET
-  lda #%11000001 ; 8n1 serial, enable DLAB
-  sta UART_LCR
-
-  lda #$00       ; Set divisor to 12 (9600 baud)
-  sta UART_DLL
-  lda #$0C
-  sta UART_DLM
-
-  lda #%11000000 ; 8n1 serial, disable DLAB
-  sta UART_LCR
-
-  lda #%01000000 ; Enable RTS
-  sta UART_MCR
-
-  lda 'H         ; send 'H'
-  sta UART_BUFR
-
-WAIT
-  sync           ; Wait for interrupts
-  nop
-  bra WAIT
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Interrupt and Reset Vectors
-;;
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-  ORG VECS_BASE
-
-VECTORS
-  fdb $0000 ; Reserved
-  fdb $0000 ; SWI3
-  fdb $0000 ; SWI2
-  fdb $0000 ; FIRQ
-  fdb $0000 ; IRQ
-  fdb $0000 ; SWI
-  fdb $0000 ; NMI
-  fdb RESET ; Reset

code/boot/src/hardware.inc

@@ -1,7 +1,9 @@
 ; CHIBI PC-09 Hardware Definitions
-; Copyright (c) 2024 Amber Zeller, Gale Faraday
+; Copyright (c) 2024-2025 Amber Zeller, Gale Faraday
 ; Licensed under MIT
 
+; vim: ft=asm
+
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;;
 ;; Hardware Base Addresses
@@ -20,23 +22,23 @@ VECS_BASE EQU $FFF0 ; Vectors Base Address
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 ; When UARTF_LCR_DLAB = 0:
-UART_BUFR EQU UART_BASE    ; TX/RX Buffer (Read for RX, Write for TX)
-UART_RBR EQU UART_BASE     ; RX Buffer Register
-UART_THR EQU UART_BASE     ; TX Holding Register
-UART_IER EQU UART_BASE + 1 ; Interrupt Enable Register
+UART_BUFR EQU UART_BASE  ; TX/RX Buffer (Read for RX, Write for TX)
+UART_RBR EQU UART_BASE   ; RX Buffer Register
+UART_THR EQU UART_BASE   ; TX Holding Register
+UART_IER EQU UART_BASE+1 ; Interrupt Enable Register
 
 ; When UARTF_LCR_DLAB = 1:
-UART_DLL EQU UART_BASE     ; Divisor Latch (LSB)
-UART_DLM EQU UART_BASE + 1 ; Divisor Latch (MSB)
+UART_DLL EQU UART_BASE   ; Divisor Latch (LSB)
+UART_DLM EQU UART_BASE+1 ; Divisor Latch (MSB)
 
 ; Independent of DLAB:
-UART_IIR EQU UART_BASE + 2 ; Interrupt Ident Register (Upon Read)
-UART_FCR EQU UART_BASE + 2 ; FIFO Control Register (Upon Write)
-UART_LCR EQU UART_BASE + 3 ; Line Control Register
-UART_MCR EQU UART_BASE + 4 ; MODEM Control Register
-UART_LSR EQU UART_BASE + 5 ; Line Status Register
-UART_MSR EQU UART_BASE + 6 ; MODEM Status Register
-UART_SCR EQU UART_BASE + 7 ; Scratch Register (Not for control just spare RAM)
+UART_IIR EQU UART_BASE+2 ; Interrupt Ident Register (Upon Read)
+UART_FCR EQU UART_BASE+2 ; FIFO Control Register (Upon Write)
+UART_LCR EQU UART_BASE+3 ; Line Control Register
+UART_MCR EQU UART_BASE+4 ; MODEM Control Register
+UART_LSR EQU UART_BASE+5 ; Line Status Register
+UART_MSR EQU UART_BASE+6 ; MODEM Status Register
+UART_SCR EQU UART_BASE+7 ; Scratch Register (Not for control just spare RAM)
 
 ; UART Flags for Interrupt Enable Register:
 UARTF_IER_ERBFI EQU %10000000 ; Enable Received Data Available Interrupt
@@ -93,4 +95,3 @@ UARTF_MSR_DSR  EQU %00000100 ; Data Set Ready
 UARTF_MSR_RI   EQU %00000010 ; Ring Indicator
 UARTF_MSR_DCD  EQU %00000001 ; Data Carrier Detect
 
-; vim: ft=asm

code/boot/src/memtest.s

@@ -0,0 +1,42 @@
+; CHIBI PC-09 Prototype #1 Boot ROM -- Memory Testing Routines
+; Copyright (c) 2024-2025 Amber Zeller, Gale Faraday
+; Licensed under MIT
+
+  INCLUDE "hardware.inc"
+  INCLUDE "serial.inc"
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Memory Testing Routines
+;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+  SECTION MEMTEST
+
+; RAM testing routine. Ported to 6809 from 6800, based on source for ROBIT-2 for
+; MIKBUG.
+RAMTEST
+  ldx #SRAM_BASE
+AGAIN@                 ; Store 1 in memory
+  lda #1               ; Set [X] to 1
+  sta 0,x
+  cmpa 0,x             ; If failed print out an error indicator
+  bne ERR@
+NEXT@                  ; Loop point for next address
+  asla                 ; Shift A and [X] left
+  asl 0,x
+  cmpa 0,x             ; Compare A and [X]
+  bne ERR@
+  cmpa #$80            ; Only test up to $80
+  bne NEXT@            ; Loop if not $80
+  cmpx #$60FF          ; Compare X to end of RAM
+  beq PASS@            ; Finish if we're at the end
+  leax 1,x             ; Increment X
+  bra AGAIN@
+ERR@                   ; Write out error indicator
+  ldb #'X
+  jsr OUTCHAR
+PASS@                  ; Pass test
+  ldb #'P
+  jsr OUTCHAR
+  rts

code/boot/src/reset.inc

@@ -0,0 +1,7 @@
+; CHIBI PC-09 Prototype #1 -- Reset Handler Header
+; Copyright (c) 2025 Amber Zeller, Gale Faraday
+; Licensed under MIT
+
+; vim: ft=asm
+
+RESET IMPORT

code/boot/src/reset.s

@@ -0,0 +1,35 @@
+; CHIBI PC-09 Prototype #1 Boot ROM -- Reset Handler
+; Copyright (c) 2024-2025 Amber Zeller, Gale Faraday
+; Licensed under MIT
+
+  INCLUDE "hardware.inc"
+  INCLUDE "serial.inc"
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Hardware Initialization Routines
+;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+  SECTION RESET
+
+  EXPORT RESET
+
+RESET
+  ; 8n1 Serial Enable DLAB
+  lda #UARTF_LCR_WLS | UARTF_LCR_DLAB
+  sta UART_LCR
+  ; REVIEW: Potential endianness hiccough here
+  ldd #$0C00           ; Set divisor to 12 (9600 baud)
+  sta UART_DLM
+  stb UART_DLL
+  lda #(UARTF_LCR_WLS) ; 8n1 serial, disable DLAB
+  sta UART_LCR
+  lda #(UARTF_MCR_RTS) ; Enable Request-to-Send
+  sta UART_MCR
+  lda #'H               ; send 'H'
+  sta UART_BUFR
+WAIT@
+  sync                 ; Wait for interrupts
+  nop
+  bra WAIT@

code/boot/src/serial.inc

@@ -0,0 +1,8 @@
+; CHIBI PC-09 Prototype #1 -- Serial Driver Header
+; Copyright (c) 2025 Amber Zeller, Gale Faraday
+; Licensed under MIT
+
+; vim: ft=asm
+
+OUTCHAR IMPORT
+OUTSTR IMPORT

code/boot/src/serial.s

@@ -0,0 +1,45 @@
+; CHIBI PC-09 Prototype #1 Boot ROM -- Serial Driver
+; Copyright (c) 2024-2025 Amber Zeller, Gale Faraday
+; Licensed under MIT
+
+  INCLUDE "hardware.inc"
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Serial UART Driver
+;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+  SECTION SERIAL
+
+  EXPORT OUTCHAR
+  EXPORT OUTSTR
+
+; Writes a char to the UART in non FIFO mode, preserves A.
+; @param b: char to write
+OUTCHAR
+  pshs a               ; Preserve A
+NOTREADY@
+  lda UART_LSR         ; if LSR.THRE == 1 then write
+  anda UARTF_LSR_THRE
+  bne NOTREADY@        ; Loop if UART not ready yet
+  stb UART_BUFR        ; Write char
+  puls a               ; Restore A
+  rts
+
+; Writes a null terminated string to the UART in non FIFO mode, clobbers A and
+; B.
+; @param x: null terminated string start address.
+OUTSTR
+  ldb 0,x              ; Get the next value from X
+  cmpb #$00            ; Make sure that we aren't at a terminator
+  beq END@
+  leax 1,x             ; Increment X for our next char
+NOTREADY@              ; Loop point for UART waiting
+  lda UART_LSR         ; Wait for UART to be ready
+  anda UARTF_LSR_THRE
+  bne NOTREADY@
+  stb UART_BUFR        ; Actually do our write
+  bra OUTSTR           ; Reset for the next char
+END@                   ; Jump point for end of routine
+  rts

code/boot/src/vecs.s

@@ -0,0 +1,23 @@
+; CHIBI PC-09 Prototype #1 Boot ROM -- Interrupt and Reset Vectors
+; Copyright (c) 2024-2025 Amber Zeller, Gale Faraday
+; Licensed under MIT
+
+  INCLUDE "reset.inc"
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Interrupt and Reset Vectors
+;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+  SECTION VECTORS
+
+VECTORS
+  fdb $0000 ; Reserved
+  fdb $0000 ; SWI3
+  fdb $0000 ; SWI2
+  fdb $0000 ; FIRQ
+  fdb $0000 ; IRQ
+  fdb $0000 ; SWI
+  fdb $0000 ; NMI
+  fdb RESET ; Reset

docs/74ls612.txt

@@ -1,6 +0,0 @@
-TTL devices can handle CMOS input. HD6309 -> 74LS612
-CMOS devices may or may not handle TTL input. 74LS612 -> peripherals
-
-62256 SRAM, 28C256 EEPROM, 16550 UART all handle TTL input.
-82C42 lists it's outputs as TTL compatible, but says nothing for inputs.
-Must ensure all peripherals are rated for TTL input.

docs/README.md

@@ -3,7 +3,6 @@
 File descriptions:
 
 - links.txt contains useful links i would like to keep
-- 6809-sn74ls612_timing.md contains notes on the mmu and cpu interface
 - tech-spec.md contains basic info on layout of system (outdated)
 - timing.html contains info on vga timing pulled from https://martin.hinner.info/vga/timing.html
 - vga_ram.txt contains notes on ram size for the vga card

pcb/.gitignore

@@ -0,0 +1 @@
+fp-info-cache

pcb/prototype-1/v1.1/prototype-1.kicad_prl

@@ -0,0 +1,131 @@
+{
+  "board": {
+    "active_layer": 0,
+    "active_layer_preset": "",
+    "auto_track_width": true,
+    "hidden_netclasses": [],
+    "hidden_nets": [],
+    "high_contrast_mode": 0,
+    "net_color_mode": 1,
+    "opacity": {
+      "images": 0.6,
+      "pads": 1.0,
+      "shapes": 1.0,
+      "tracks": 1.0,
+      "vias": 1.0,
+      "zones": 0.6
+    },
+    "selection_filter": {
+      "dimensions": true,
+      "footprints": true,
+      "graphics": true,
+      "keepouts": true,
+      "lockedItems": false,
+      "otherItems": true,
+      "pads": true,
+      "text": true,
+      "tracks": true,
+      "vias": true,
+      "zones": true
+    },
+    "visible_items": [
+      "vias",
+      "footprint_text",
+      "footprint_anchors",
+      "ratsnest",
+      "grid",
+      "footprints_front",
+      "footprints_back",
+      "footprint_values",
+      "footprint_references",
+      "tracks",
+      "drc_errors",
+      "drawing_sheet",
+      "bitmaps",
+      "pads",
+      "zones",
+      "drc_warnings",
+      "drc_exclusions",
+      "locked_item_shadows",
+      "conflict_shadows",
+      "shapes"
+    ],
+    "visible_layers": "ffffffff_ffffffff_ffffffff_ffffffff",
+    "zone_display_mode": 1
+  },
+  "git": {
+    "repo_type": "",
+    "repo_username": "",
+    "ssh_key": ""
+  },
+  "meta": {
+    "filename": "prototype-1.kicad_prl",
+    "version": 5
+  },
+  "net_inspector_panel": {
+    "col_hidden": [
+      false,
+      false,
+      false,
+      false,
+      false,
+      false,
+      false,
+      false,
+      false,
+      false
+    ],
+    "col_order": [
+      0,
+      1,
+      2,
+      3,
+      4,
+      5,
+      6,
+      7,
+      8,
+      9
+    ],
+    "col_widths": [
+      0,
+      0,
+      0,
+      0,
+      0,
+      0,
+      0,
+      0,
+      0,
+      0
+    ],
+    "custom_group_rules": [],
+    "expanded_rows": [],
+    "filter_by_net_name": true,
+    "filter_by_netclass": true,
+    "filter_text": "",
+    "group_by_constraint": false,
+    "group_by_netclass": false,
+    "show_unconnected_nets": false,
+    "show_zero_pad_nets": false,
+    "sort_ascending": true,
+    "sorting_column": 0
+  },
+  "open_jobsets": [],
+  "project": {
+    "files": []
+  },
+  "schematic": {
+    "selection_filter": {
+      "graphics": true,
+      "images": true,
+      "labels": true,
+      "lockedItems": false,
+      "otherItems": true,
+      "pins": true,
+      "symbols": true,
+      "text": true,
+      "wires": true
+    }
+  }
+}

pcb/prototype-1/v1.1/prototype-1.kicad_pro

@@ -0,0 +1,639 @@
+{
+  "board": {
+    "3dviewports": [],
+    "design_settings": {
+      "defaults": {
+        "apply_defaults_to_fp_fields": false,
+        "apply_defaults_to_fp_shapes": false,
+        "apply_defaults_to_fp_text": false,
+        "board_outline_line_width": 0.05,
+        "copper_line_width": 0.2,
+        "copper_text_italic": false,
+        "copper_text_size_h": 1.5,
+        "copper_text_size_v": 1.5,
+        "copper_text_thickness": 0.3,
+        "copper_text_upright": false,
+        "courtyard_line_width": 0.05,
+        "dimension_precision": 4,
+        "dimension_units": 3,
+        "dimensions": {
+          "arrow_length": 1270000,
+          "extension_offset": 500000,
+          "keep_text_aligned": true,
+          "suppress_zeroes": false,
+          "text_position": 0,
+          "units_format": 1
+        },
+        "fab_line_width": 0.1,
+        "fab_text_italic": false,
+        "fab_text_size_h": 1.0,
+        "fab_text_size_v": 1.0,
+        "fab_text_thickness": 0.15,
+        "fab_text_upright": false,
+        "other_line_width": 0.1,
+        "other_text_italic": false,
+        "other_text_size_h": 1.0,
+        "other_text_size_v": 1.0,
+        "other_text_thickness": 0.15,
+        "other_text_upright": false,
+        "pads": {
+          "drill": 0.762,
+          "height": 1.524,
+          "width": 1.524
+        },
+        "silk_line_width": 0.1,
+        "silk_text_italic": false,
+        "silk_text_size_h": 1.0,
+        "silk_text_size_v": 1.0,
+        "silk_text_thickness": 0.1,
+        "silk_text_upright": false,
+        "zones": {
+          "min_clearance": 0.5
+        }
+      },
+      "diff_pair_dimensions": [
+        {
+          "gap": 0.0,
+          "via_gap": 0.0,
+          "width": 0.0
+        }
+      ],
+      "drc_exclusions": [],
+      "meta": {
+        "version": 2
+      },
+      "rule_severities": {
+        "annular_width": "error",
+        "clearance": "error",
+        "connection_width": "warning",
+        "copper_edge_clearance": "error",
+        "copper_sliver": "warning",
+        "courtyards_overlap": "error",
+        "creepage": "error",
+        "diff_pair_gap_out_of_range": "error",
+        "diff_pair_uncoupled_length_too_long": "error",
+        "drill_out_of_range": "error",
+        "duplicate_footprints": "warning",
+        "extra_footprint": "warning",
+        "footprint": "error",
+        "footprint_filters_mismatch": "ignore",
+        "footprint_symbol_mismatch": "warning",
+        "footprint_type_mismatch": "ignore",
+        "hole_clearance": "error",
+        "hole_near_hole": "error",
+        "hole_to_hole": "error",
+        "holes_co_located": "warning",
+        "invalid_outline": "error",
+        "isolated_copper": "warning",
+        "item_on_disabled_layer": "error",
+        "items_not_allowed": "error",
+        "length_out_of_range": "error",
+        "lib_footprint_issues": "warning",
+        "lib_footprint_mismatch": "warning",
+        "malformed_courtyard": "error",
+        "microvia_drill_out_of_range": "error",
+        "mirrored_text_on_front_layer": "warning",
+        "missing_courtyard": "ignore",
+        "missing_footprint": "warning",
+        "net_conflict": "warning",
+        "nonmirrored_text_on_back_layer": "warning",
+        "npth_inside_courtyard": "ignore",
+        "padstack": "warning",
+        "pth_inside_courtyard": "ignore",
+        "shorting_items": "error",
+        "silk_edge_clearance": "warning",
+        "silk_over_copper": "warning",
+        "silk_overlap": "warning",
+        "skew_out_of_range": "error",
+        "solder_mask_bridge": "error",
+        "starved_thermal": "error",
+        "text_height": "warning",
+        "text_on_edge_cuts": "error",
+        "text_thickness": "warning",
+        "through_hole_pad_without_hole": "error",
+        "too_many_vias": "error",
+        "track_angle": "error",
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+      "distpn": "",
+      "internal_id": "",
+      "mfg": "",
+      "mpn": ""
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+      "bus_to_net_conflict": "error",
+      "conflicting_netclasses": "error",
+      "different_unit_footprint": "error",
+      "different_unit_net": "error",
+      "duplicate_reference": "error",
+      "duplicate_sheet_names": "error",
+      "endpoint_off_grid": "warning",
+      "extra_units": "error",
+      "footprint_filter": "ignore",
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+      "four_way_junction": "ignore",
+      "global_label_dangling": "warning",
+      "hier_label_mismatch": "error",
+      "label_dangling": "error",
+      "label_multiple_wires": "warning",
+      "lib_symbol_issues": "warning",
+      "lib_symbol_mismatch": "warning",
+      "missing_bidi_pin": "warning",
+      "missing_input_pin": "warning",
+      "missing_power_pin": "error",
+      "missing_unit": "warning",
+      "multiple_net_names": "warning",
+      "net_not_bus_member": "warning",
+      "no_connect_connected": "warning",
+      "no_connect_dangling": "warning",
+      "pin_not_connected": "error",
+      "pin_not_driven": "error",
+      "pin_to_pin": "error",
+      "power_pin_not_driven": "error",
+      "same_local_global_label": "warning",
+      "similar_label_and_power": "warning",
+      "similar_labels": "warning",
+      "similar_power": "warning",
+      "simulation_model_issue": "ignore",
+      "single_global_label": "ignore",
+      "unannotated": "error",
+      "unconnected_wire_endpoint": "warning",
+      "unit_value_mismatch": "error",
+      "unresolved_variable": "error",
+      "wire_dangling": "error"
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+        "name": "Default",
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+        "schematic_color": "rgba(0, 0, 0, 0.000)",
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+        "via_drill": 0.3,
+        "wire_width": 6
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+    "netclass_patterns": []
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+      "idf": "",
+      "netlist": "",
+      "plot": "output/gerber/",
+      "pos_files": "",
+      "specctra_dsn": "",
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+      "name": "CSV",
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+      "string_delimiter": "\""
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+          "name": "Datasheet",
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+          "label": "Footprint",
+          "name": "Footprint",
+          "show": true
+        },
+        {
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+          "label": "Qty",
+          "name": "${QUANTITY}",
+          "show": true
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+        {
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+          "label": "DNP",
+          "name": "${DNP}",
+          "show": true
+        },
+        {
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+          "label": "#",
+          "name": "${ITEM_NUMBER}",
+          "show": false
+        },
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+          "label": "Description",
+          "name": "Description",
+          "show": false
+        }
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+      "include_excluded_from_bom": false,
+      "name": "",
+      "sort_asc": true,
+      "sort_field": "Reference"
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+    "plot_directory": "",
+    "space_save_all_events": true,
+    "spice_current_sheet_as_root": false,
+    "spice_external_command": "spice \"%I\"",
+    "spice_model_current_sheet_as_root": true,
+    "spice_save_all_currents": false,
+    "spice_save_all_dissipations": false,
+    "spice_save_all_voltages": false,
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+  "text_variables": {}
+}