feat\!: migrate to LWTOOLS build system
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3
code/boot/linkscript
Normal file
3
code/boot/linkscript
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@@ -0,0 +1,3 @@
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section CODE load 8000
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section VECTORS high 100000
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@@ -8,26 +8,45 @@
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# Project Defaults & Folders
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# ------------------------------------------------------------------------------
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TARGET := boot.bin
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TARGET := boot
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TARGROM := $(TARGET).bin
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SRCDIR := src/
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MAINSRC := $(SRCDIR)boot.s
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BUILDDIR := build/
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SRCS := $(wildcard $(SRCDIR)*.s)
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OBJS := $(patsubst $(SRCDIR)%.s,$(BUILDDIR)%.o,$(SRCS))
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INCS := $(wildcard $(SRCDIR)*.inc)
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# ------------------------------------------------------------------------------
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# Toolchain Definitions
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# ------------------------------------------------------------------------------
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AS := asm6809
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AS := lwasm
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LD := lwlink
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FIX := mot2bin
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ASFLAGS := -f obj
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LDFLAGS := -f srec -m map.txt -s linkscript
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# ------------------------------------------------------------------------------
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# Rules and Phony Targets
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# ------------------------------------------------------------------------------
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all: $(TARGET)
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all: $(TARGROM)
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$(TARGET): $(SRCS) $(INCS)
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$(AS) -o $(TARGET) $(MAINSRC)
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# Fix srec into flashable bin file
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$(TARGROM): $(TARGET).s19
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$(FIX) -out $@ $<
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# Link objects
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$(TARGET).s19: $(OBJS)
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$(LD) $(LDFLAGS) -o $@ $<
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# Assemble objects
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$(OBJS): $(BUILDDIR)%.o : $(SRCDIR)%.s
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-@mkdir -p $(BUILDDIR)
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$(AS) $(ASFLAGS) -o $@ $<
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.IGNORE: clean
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clean:
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rm -v $(TARGET)
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@echo 'Cleaning up intermediary files...'
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@rm -rv $(TARGROM) $(TARGET).s19 $(BUILDDIR)
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@@ -2,7 +2,7 @@
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; Copyright (c) 2024 Amber Zeller, Gale Faraday
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; Licensed under MIT
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INCLUDE "src/hardware.inc"
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INCLUDE "hardware.inc"
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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@@ -10,12 +10,12 @@
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;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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SECTION "Reset"
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ORG ROM_BASE
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SECTION CODE
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;ORG ROM_BASE
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RESET
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; 8n1 Serial Enable DLAB
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lda #(UARTF_LCR_WLS | UARTF_LCR_DLAB)
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lda #UARTF_LCR_WLS | UARTF_LCR_DLAB
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sta UART_LCR
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; REVIEW: Potential endianness hiccough here
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@@ -29,7 +29,7 @@ RESET
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lda #(UARTF_MCR_RTS) ; Enable Request-to-Send
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sta UART_MCR
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lda 'H ; send 'H'
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lda #'H ; send 'H'
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sta UART_BUFR
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WAIT
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@@ -37,16 +37,16 @@ WAIT
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nop
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bra WAIT
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SECTION "Serial"
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;SECTION "Serial"
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; Writes a char to the UART in non FIFO mode, preserves A.
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; @param b: char to write
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OUTCHAR
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pshs a ; Preserve A
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1
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NOTREADY@
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lda UART_LSR ; if LSR.THRE == 1 then write
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anda UARTF_LSR_THRE
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bne 1B ; Loop if UART not ready yet
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bne NOTREADY@ ; Loop if UART not ready yet
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stb UART_BUFR ; Write char
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puls a ; Restore A
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rts
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@@ -55,45 +55,45 @@ OUTCHAR
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; B.
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; @param x: null terminated string start address.
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OUTSTR
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ldb x ; Get the next value from X
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cmpb #$00 ; Make sure that mother is non-null
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beq 2F
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ldb 0,x ; Get the next value from X
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cmpb #$00 ; Make sure that we aren't at a terminator
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beq END@
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leax 1,x ; Increment X for our next char
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1 ; Loop point for UART waiting
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NOTREADY@ ; Loop point for UART waiting
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lda UART_LSR ; Wait for UART to be ready
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anda UARTF_LSR_THRE
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bne 1B
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bne NOTREADY@
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stb UART_BUFR ; Actually do our write
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bra OUTSTR ; Reset for the next char
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2 ; Jump point for end of routine
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END@ ; Jump point for end of routine
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rts
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SECTION "Memtest"
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;SECTION "Memtest"
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; RAM testing routine. Ported to 6809 from 6800, based on source for ROBIT-2 for
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; MIKBUG.
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RAMTEST
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ldx #SRAM_BASE
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1 ; Store 1 in memory
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AGAIN@ ; Store 1 in memory
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lda #1 ; Set [X] to 1
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sta 0,x
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cmpa 0,x ; If failed print out an error indicator
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bne 3F
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2 ; Loop point for next address
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bne ERR@
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NEXT@ ; Loop point for next address
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asla ; Shift A and [X] left
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asl 0,x
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cmpa 0,x ; Compare A and [X]
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bne 3F
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bne ERR@
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cmpa #$80 ; Only test up to $80
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bne 2B ; Loop if not $80
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bne NEXT@ ; Loop if not $80
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cmpx #$60FF ; Compare X to end of RAM
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beq 4F ; Finish if we're at the end
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beq PASS@ ; Finish if we're at the end
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leax 1,x ; Increment X
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bra 1B
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3 ; Write out error indicator
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bra AGAIN@
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ERR@ ; Write out error indicator
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ldb #'X
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jsr OUTCHAR
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4 ; Pass test
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PASS@ ; Pass test
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ldb #'P
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jsr OUTCHAR
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rts
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@@ -104,8 +104,8 @@ RAMTEST
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;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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SECTION "Vectors"
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ORG VECS_BASE
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SECTION VECTORS
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;ORG VECS_BASE
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VECTORS
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fdb $0000 ; Reserved
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@@ -1,7 +1,9 @@
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; CHIBI PC-09 Hardware Definitions
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; Copyright (c) 2024 Amber Zeller, Gale Faraday
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; Copyright (c) 2024-2025 Amber Zeller, Gale Faraday
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; Licensed under MIT
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; vim: ft=asm
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; Hardware Base Addresses
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@@ -20,23 +22,23 @@ VECS_BASE EQU $FFF0 ; Vectors Base Address
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; When UARTF_LCR_DLAB = 0:
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UART_BUFR EQU UART_BASE ; TX/RX Buffer (Read for RX, Write for TX)
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UART_RBR EQU UART_BASE ; RX Buffer Register
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UART_THR EQU UART_BASE ; TX Holding Register
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UART_IER EQU UART_BASE + 1 ; Interrupt Enable Register
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UART_BUFR EQU UART_BASE ; TX/RX Buffer (Read for RX, Write for TX)
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UART_RBR EQU UART_BASE ; RX Buffer Register
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UART_THR EQU UART_BASE ; TX Holding Register
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UART_IER EQU UART_BASE+1 ; Interrupt Enable Register
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; When UARTF_LCR_DLAB = 1:
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UART_DLL EQU UART_BASE ; Divisor Latch (LSB)
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UART_DLM EQU UART_BASE + 1 ; Divisor Latch (MSB)
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UART_DLL EQU UART_BASE ; Divisor Latch (LSB)
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UART_DLM EQU UART_BASE+1 ; Divisor Latch (MSB)
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; Independent of DLAB:
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UART_IIR EQU UART_BASE + 2 ; Interrupt Ident Register (Upon Read)
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UART_FCR EQU UART_BASE + 2 ; FIFO Control Register (Upon Write)
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UART_LCR EQU UART_BASE + 3 ; Line Control Register
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UART_MCR EQU UART_BASE + 4 ; MODEM Control Register
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UART_LSR EQU UART_BASE + 5 ; Line Status Register
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UART_MSR EQU UART_BASE + 6 ; MODEM Status Register
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UART_SCR EQU UART_BASE + 7 ; Scratch Register (Not for control just spare RAM)
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UART_IIR EQU UART_BASE+2 ; Interrupt Ident Register (Upon Read)
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UART_FCR EQU UART_BASE+2 ; FIFO Control Register (Upon Write)
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UART_LCR EQU UART_BASE+3 ; Line Control Register
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UART_MCR EQU UART_BASE+4 ; MODEM Control Register
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UART_LSR EQU UART_BASE+5 ; Line Status Register
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UART_MSR EQU UART_BASE+6 ; MODEM Status Register
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UART_SCR EQU UART_BASE+7 ; Scratch Register (Not for control just spare RAM)
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; UART Flags for Interrupt Enable Register:
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UARTF_IER_ERBFI EQU %10000000 ; Enable Received Data Available Interrupt
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@@ -93,4 +95,3 @@ UARTF_MSR_DSR EQU %00000100 ; Data Set Ready
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UARTF_MSR_RI EQU %00000010 ; Ring Indicator
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UARTF_MSR_DCD EQU %00000001 ; Data Carrier Detect
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; vim: ft=asm
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