diff --git a/code/boot/linkscript b/code/boot/linkscript
new file mode 100644
index 0000000..4bfb66f
--- /dev/null
+++ b/code/boot/linkscript
@@ -0,0 +1,3 @@
+section CODE load 8000
+
+section VECTORS high 100000
diff --git a/code/boot/makefile b/code/boot/makefile
index e7f03d3..81b3316 100644
--- a/code/boot/makefile
+++ b/code/boot/makefile
@@ -8,26 +8,45 @@
 # Project Defaults & Folders
 # ------------------------------------------------------------------------------
 
-TARGET  := boot.bin
+TARGET  := boot
+TARGROM := $(TARGET).bin
 SRCDIR  := src/
-MAINSRC := $(SRCDIR)boot.s
+BUILDDIR := build/
 SRCS    := $(wildcard $(SRCDIR)*.s)
+OBJS    := $(patsubst $(SRCDIR)%.s,$(BUILDDIR)%.o,$(SRCS))
 INCS    := $(wildcard $(SRCDIR)*.inc)
 
 # ------------------------------------------------------------------------------
 # Toolchain Definitions
 # ------------------------------------------------------------------------------
 
-AS := asm6809
+AS  := lwasm
+LD  := lwlink
+FIX := mot2bin
+
+ASFLAGS := -f obj
+LDFLAGS := -f srec -m map.txt -s linkscript
 
 # ------------------------------------------------------------------------------
 # Rules and Phony Targets
 # ------------------------------------------------------------------------------
 
-all: $(TARGET)
+all: $(TARGROM)
 
-$(TARGET): $(SRCS) $(INCS)
-	$(AS) -o $(TARGET) $(MAINSRC)
+# Fix srec into flashable bin file
+$(TARGROM): $(TARGET).s19
+	$(FIX) -out $@ $<
 
+# Link objects
+$(TARGET).s19: $(OBJS)
+	$(LD) $(LDFLAGS) -o $@ $<
+
+# Assemble objects
+$(OBJS): $(BUILDDIR)%.o : $(SRCDIR)%.s
+	-@mkdir -p $(BUILDDIR)
+	$(AS) $(ASFLAGS) -o $@ $<
+
+.IGNORE: clean
 clean:
-	rm -v $(TARGET)
+	@echo 'Cleaning up intermediary files...'
+	@rm -rv $(TARGROM) $(TARGET).s19 $(BUILDDIR)
diff --git a/code/boot/src/boot.s b/code/boot/src/boot.s
index 408ced3..5c31e6d 100644
--- a/code/boot/src/boot.s
+++ b/code/boot/src/boot.s
@@ -2,7 +2,7 @@
 ; Copyright (c) 2024 Amber Zeller, Gale Faraday
 ; Licensed under MIT
 
-  INCLUDE "src/hardware.inc"
+  INCLUDE "hardware.inc"
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;;
@@ -10,12 +10,12 @@
 ;;
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
-  SECTION "Reset"
-  ORG ROM_BASE
+  SECTION CODE
+  ;ORG ROM_BASE
 
 RESET
   ; 8n1 Serial Enable DLAB
-  lda #(UARTF_LCR_WLS | UARTF_LCR_DLAB)
+  lda #UARTF_LCR_WLS | UARTF_LCR_DLAB
   sta UART_LCR
 
   ; REVIEW: Potential endianness hiccough here
@@ -29,7 +29,7 @@ RESET
   lda #(UARTF_MCR_RTS) ; Enable Request-to-Send
   sta UART_MCR
 
-  lda 'H               ; send 'H'
+  lda #'H               ; send 'H'
   sta UART_BUFR
 
 WAIT
@@ -37,16 +37,16 @@ WAIT
   nop
   bra WAIT
 
-  SECTION "Serial"
+  ;SECTION "Serial"
 
 ; Writes a char to the UART in non FIFO mode, preserves A.
 ; @param b: char to write
 OUTCHAR
   pshs a               ; Preserve A
-1
+NOTREADY@
   lda UART_LSR         ; if LSR.THRE == 1 then write
   anda UARTF_LSR_THRE
-  bne 1B               ; Loop if UART not ready yet
+  bne NOTREADY@        ; Loop if UART not ready yet
   stb UART_BUFR        ; Write char
   puls a               ; Restore A
   rts
@@ -55,45 +55,45 @@ OUTCHAR
 ; B.
 ; @param x: null terminated string start address.
 OUTSTR
-  ldb x                ; Get the next value from X
-  cmpb #$00            ; Make sure that mother is non-null
-  beq 2F
+  ldb 0,x              ; Get the next value from X
+  cmpb #$00            ; Make sure that we aren't at a terminator
+  beq END@
   leax 1,x             ; Increment X for our next char
-1                      ; Loop point for UART waiting
+NOTREADY@              ; Loop point for UART waiting
   lda UART_LSR         ; Wait for UART to be ready
   anda UARTF_LSR_THRE
-  bne 1B
+  bne NOTREADY@
   stb UART_BUFR        ; Actually do our write
   bra OUTSTR           ; Reset for the next char
-2                      ; Jump point for end of routine
+END@                   ; Jump point for end of routine
   rts
 
-  SECTION "Memtest"
+  ;SECTION "Memtest"
 
 ; RAM testing routine. Ported to 6809 from 6800, based on source for ROBIT-2 for
 ; MIKBUG.
 RAMTEST
   ldx #SRAM_BASE
-1                      ; Store 1 in memory
+AGAIN@                 ; Store 1 in memory
   lda #1               ; Set [X] to 1
   sta 0,x
   cmpa 0,x             ; If failed print out an error indicator
-  bne 3F
-2                      ; Loop point for next address
+  bne ERR@
+NEXT@                  ; Loop point for next address
   asla                 ; Shift A and [X] left
   asl 0,x
   cmpa 0,x             ; Compare A and [X]
-  bne 3F
+  bne ERR@
   cmpa #$80            ; Only test up to $80
-  bne 2B               ; Loop if not $80
+  bne NEXT@            ; Loop if not $80
   cmpx #$60FF          ; Compare X to end of RAM
-  beq 4F               ; Finish if we're at the end
+  beq PASS@            ; Finish if we're at the end
   leax 1,x             ; Increment X
-  bra 1B
-3                      ; Write out error indicator
+  bra AGAIN@
+ERR@                   ; Write out error indicator
   ldb #'X
   jsr OUTCHAR
-4                      ; Pass test
+PASS@                  ; Pass test
   ldb #'P
   jsr OUTCHAR
   rts
@@ -104,8 +104,8 @@ RAMTEST
 ;;
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
-  SECTION "Vectors"
-  ORG VECS_BASE
+  SECTION VECTORS
+  ;ORG VECS_BASE
 
 VECTORS
   fdb $0000 ; Reserved
diff --git a/code/boot/src/hardware.inc b/code/boot/src/hardware.inc
index 0049d02..fcbe629 100644
--- a/code/boot/src/hardware.inc
+++ b/code/boot/src/hardware.inc
@@ -1,7 +1,9 @@
 ; CHIBI PC-09 Hardware Definitions
-; Copyright (c) 2024 Amber Zeller, Gale Faraday
+; Copyright (c) 2024-2025 Amber Zeller, Gale Faraday
 ; Licensed under MIT
 
+; vim: ft=asm
+
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;;
 ;; Hardware Base Addresses
@@ -20,23 +22,23 @@ VECS_BASE EQU $FFF0 ; Vectors Base Address
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 ; When UARTF_LCR_DLAB = 0:
-UART_BUFR EQU UART_BASE    ; TX/RX Buffer (Read for RX, Write for TX)
-UART_RBR EQU UART_BASE     ; RX Buffer Register
-UART_THR EQU UART_BASE     ; TX Holding Register
-UART_IER EQU UART_BASE + 1 ; Interrupt Enable Register
+UART_BUFR EQU UART_BASE  ; TX/RX Buffer (Read for RX, Write for TX)
+UART_RBR EQU UART_BASE   ; RX Buffer Register
+UART_THR EQU UART_BASE   ; TX Holding Register
+UART_IER EQU UART_BASE+1 ; Interrupt Enable Register
 
 ; When UARTF_LCR_DLAB = 1:
-UART_DLL EQU UART_BASE     ; Divisor Latch (LSB)
-UART_DLM EQU UART_BASE + 1 ; Divisor Latch (MSB)
+UART_DLL EQU UART_BASE   ; Divisor Latch (LSB)
+UART_DLM EQU UART_BASE+1 ; Divisor Latch (MSB)
 
 ; Independent of DLAB:
-UART_IIR EQU UART_BASE + 2 ; Interrupt Ident Register (Upon Read)
-UART_FCR EQU UART_BASE + 2 ; FIFO Control Register (Upon Write)
-UART_LCR EQU UART_BASE + 3 ; Line Control Register
-UART_MCR EQU UART_BASE + 4 ; MODEM Control Register
-UART_LSR EQU UART_BASE + 5 ; Line Status Register
-UART_MSR EQU UART_BASE + 6 ; MODEM Status Register
-UART_SCR EQU UART_BASE + 7 ; Scratch Register (Not for control just spare RAM)
+UART_IIR EQU UART_BASE+2 ; Interrupt Ident Register (Upon Read)
+UART_FCR EQU UART_BASE+2 ; FIFO Control Register (Upon Write)
+UART_LCR EQU UART_BASE+3 ; Line Control Register
+UART_MCR EQU UART_BASE+4 ; MODEM Control Register
+UART_LSR EQU UART_BASE+5 ; Line Status Register
+UART_MSR EQU UART_BASE+6 ; MODEM Status Register
+UART_SCR EQU UART_BASE+7 ; Scratch Register (Not for control just spare RAM)
 
 ; UART Flags for Interrupt Enable Register:
 UARTF_IER_ERBFI EQU %10000000 ; Enable Received Data Available Interrupt
@@ -93,4 +95,3 @@ UARTF_MSR_DSR  EQU %00000100 ; Data Set Ready
 UARTF_MSR_RI   EQU %00000010 ; Ring Indicator
 UARTF_MSR_DCD  EQU %00000001 ; Data Carrier Detect
 
-; vim: ft=asm