feat: modularized with lwtools build system
This commit is contained in:
@@ -1,3 +1,5 @@
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section CODE load 8000
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section RESET load 8000
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section SERIAL
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section MEMTEST
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section VECTORS high 100000
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@@ -39,7 +39,7 @@ $(TARGROM): $(TARGET).s19
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# Link objects
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$(TARGET).s19: $(OBJS)
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$(LD) $(LDFLAGS) -o $@ $<
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$(LD) $(LDFLAGS) -o $@ $^
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# Assemble objects
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$(OBJS): $(BUILDDIR)%.o : $(SRCDIR)%.s
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@@ -1,118 +0,0 @@
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; CHIBI PC-09 Prototype #1 Boot ROM -- Hardware Initialization and Reset Vecs
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; Copyright (c) 2024 Amber Zeller, Gale Faraday
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; Licensed under MIT
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INCLUDE "hardware.inc"
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; Hardware Initialization Routines
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;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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SECTION CODE
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;ORG ROM_BASE
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RESET
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; 8n1 Serial Enable DLAB
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lda #UARTF_LCR_WLS | UARTF_LCR_DLAB
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sta UART_LCR
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; REVIEW: Potential endianness hiccough here
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ldd #$0C00 ; Set divisor to 12 (9600 baud)
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sta UART_DLM
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stb UART_DLL
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lda #(UARTF_LCR_WLS) ; 8n1 serial, disable DLAB
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sta UART_LCR
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lda #(UARTF_MCR_RTS) ; Enable Request-to-Send
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sta UART_MCR
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lda #'H ; send 'H'
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sta UART_BUFR
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WAIT
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sync ; Wait for interrupts
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nop
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bra WAIT
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;SECTION "Serial"
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; Writes a char to the UART in non FIFO mode, preserves A.
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; @param b: char to write
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OUTCHAR
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pshs a ; Preserve A
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NOTREADY@
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lda UART_LSR ; if LSR.THRE == 1 then write
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anda UARTF_LSR_THRE
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bne NOTREADY@ ; Loop if UART not ready yet
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stb UART_BUFR ; Write char
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puls a ; Restore A
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rts
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; Writes a null terminated string to the UART in non FIFO mode, clobbers A and
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; B.
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; @param x: null terminated string start address.
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OUTSTR
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ldb 0,x ; Get the next value from X
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cmpb #$00 ; Make sure that we aren't at a terminator
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beq END@
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leax 1,x ; Increment X for our next char
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NOTREADY@ ; Loop point for UART waiting
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lda UART_LSR ; Wait for UART to be ready
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anda UARTF_LSR_THRE
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bne NOTREADY@
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stb UART_BUFR ; Actually do our write
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bra OUTSTR ; Reset for the next char
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END@ ; Jump point for end of routine
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rts
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;SECTION "Memtest"
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; RAM testing routine. Ported to 6809 from 6800, based on source for ROBIT-2 for
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; MIKBUG.
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RAMTEST
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ldx #SRAM_BASE
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AGAIN@ ; Store 1 in memory
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lda #1 ; Set [X] to 1
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sta 0,x
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cmpa 0,x ; If failed print out an error indicator
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bne ERR@
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NEXT@ ; Loop point for next address
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asla ; Shift A and [X] left
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asl 0,x
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cmpa 0,x ; Compare A and [X]
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bne ERR@
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cmpa #$80 ; Only test up to $80
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bne NEXT@ ; Loop if not $80
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cmpx #$60FF ; Compare X to end of RAM
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beq PASS@ ; Finish if we're at the end
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leax 1,x ; Increment X
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bra AGAIN@
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ERR@ ; Write out error indicator
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ldb #'X
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jsr OUTCHAR
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PASS@ ; Pass test
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ldb #'P
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jsr OUTCHAR
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rts
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; Interrupt and Reset Vectors
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;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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SECTION VECTORS
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;ORG VECS_BASE
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VECTORS
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fdb $0000 ; Reserved
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fdb $0000 ; SWI3
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fdb $0000 ; SWI2
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fdb $0000 ; FIRQ
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fdb $0000 ; IRQ
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fdb $0000 ; SWI
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fdb $0000 ; NMI
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fdb RESET ; Reset
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42
code/boot/src/memtest.s
Normal file
42
code/boot/src/memtest.s
Normal file
@@ -0,0 +1,42 @@
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; CHIBI PC-09 Prototype #1 Boot ROM -- Memory Testing Routines
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; Copyright (c) 2024-2025 Amber Zeller, Gale Faraday
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; Licensed under MIT
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INCLUDE "hardware.inc"
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INCLUDE "serial.inc"
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; Memory Testing Routines
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;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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SECTION MEMTEST
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; RAM testing routine. Ported to 6809 from 6800, based on source for ROBIT-2 for
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; MIKBUG.
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RAMTEST
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ldx #SRAM_BASE
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AGAIN@ ; Store 1 in memory
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lda #1 ; Set [X] to 1
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sta 0,x
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cmpa 0,x ; If failed print out an error indicator
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bne ERR@
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NEXT@ ; Loop point for next address
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asla ; Shift A and [X] left
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asl 0,x
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cmpa 0,x ; Compare A and [X]
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bne ERR@
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cmpa #$80 ; Only test up to $80
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bne NEXT@ ; Loop if not $80
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cmpx #$60FF ; Compare X to end of RAM
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beq PASS@ ; Finish if we're at the end
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leax 1,x ; Increment X
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bra AGAIN@
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ERR@ ; Write out error indicator
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ldb #'X
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jsr OUTCHAR
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PASS@ ; Pass test
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ldb #'P
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jsr OUTCHAR
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rts
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7
code/boot/src/reset.inc
Normal file
7
code/boot/src/reset.inc
Normal file
@@ -0,0 +1,7 @@
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; CHIBI PC-09 Prototype #1 -- Reset Handler Header
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; Copyright (c) 2025 Amber Zeller, Gale Faraday
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; Licensed under MIT
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; vim: ft=asm
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RESET IMPORT
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35
code/boot/src/reset.s
Normal file
35
code/boot/src/reset.s
Normal file
@@ -0,0 +1,35 @@
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; CHIBI PC-09 Prototype #1 Boot ROM -- Reset Handler
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; Copyright (c) 2024-2025 Amber Zeller, Gale Faraday
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; Licensed under MIT
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INCLUDE "hardware.inc"
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INCLUDE "serial.inc"
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; Hardware Initialization Routines
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;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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SECTION RESET
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EXPORT RESET
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RESET
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; 8n1 Serial Enable DLAB
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lda #UARTF_LCR_WLS | UARTF_LCR_DLAB
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sta UART_LCR
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; REVIEW: Potential endianness hiccough here
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ldd #$0C00 ; Set divisor to 12 (9600 baud)
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sta UART_DLM
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stb UART_DLL
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lda #(UARTF_LCR_WLS) ; 8n1 serial, disable DLAB
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sta UART_LCR
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lda #(UARTF_MCR_RTS) ; Enable Request-to-Send
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sta UART_MCR
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lda #'H ; send 'H'
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sta UART_BUFR
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WAIT@
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sync ; Wait for interrupts
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nop
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bra WAIT@
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8
code/boot/src/serial.inc
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8
code/boot/src/serial.inc
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@@ -0,0 +1,8 @@
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; CHIBI PC-09 Prototype #1 -- Serial Driver Header
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; Copyright (c) 2025 Amber Zeller, Gale Faraday
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; Licensed under MIT
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; vim: ft=asm
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OUTCHAR IMPORT
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OUTSTR IMPORT
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45
code/boot/src/serial.s
Normal file
45
code/boot/src/serial.s
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@@ -0,0 +1,45 @@
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; CHIBI PC-09 Prototype #1 Boot ROM -- Serial Driver
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; Copyright (c) 2024-2025 Amber Zeller, Gale Faraday
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; Licensed under MIT
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INCLUDE "hardware.inc"
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; Serial UART Driver
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;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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SECTION SERIAL
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EXPORT OUTCHAR
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EXPORT OUTSTR
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; Writes a char to the UART in non FIFO mode, preserves A.
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; @param b: char to write
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OUTCHAR
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pshs a ; Preserve A
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NOTREADY@
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lda UART_LSR ; if LSR.THRE == 1 then write
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anda UARTF_LSR_THRE
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bne NOTREADY@ ; Loop if UART not ready yet
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stb UART_BUFR ; Write char
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puls a ; Restore A
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rts
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; Writes a null terminated string to the UART in non FIFO mode, clobbers A and
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; B.
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; @param x: null terminated string start address.
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OUTSTR
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ldb 0,x ; Get the next value from X
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cmpb #$00 ; Make sure that we aren't at a terminator
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beq END@
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leax 1,x ; Increment X for our next char
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NOTREADY@ ; Loop point for UART waiting
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lda UART_LSR ; Wait for UART to be ready
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anda UARTF_LSR_THRE
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bne NOTREADY@
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stb UART_BUFR ; Actually do our write
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bra OUTSTR ; Reset for the next char
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END@ ; Jump point for end of routine
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rts
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23
code/boot/src/vecs.s
Normal file
23
code/boot/src/vecs.s
Normal file
@@ -0,0 +1,23 @@
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; CHIBI PC-09 Prototype #1 Boot ROM -- Interrupt and Reset Vectors
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; Copyright (c) 2024-2025 Amber Zeller, Gale Faraday
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; Licensed under MIT
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INCLUDE "reset.inc"
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; Interrupt and Reset Vectors
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;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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SECTION VECTORS
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VECTORS
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fdb $0000 ; Reserved
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fdb $0000 ; SWI3
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fdb $0000 ; SWI2
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fdb $0000 ; FIRQ
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fdb $0000 ; IRQ
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fdb $0000 ; SWI
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fdb $0000 ; NMI
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fdb RESET ; Reset
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