feat: modularized with lwtools build system

This commit is contained in:
2025-08-31 14:42:14 -05:00
parent c67176e99a
commit 677b3cb02d
9 changed files with 164 additions and 120 deletions

View File

@@ -1,3 +1,5 @@
section CODE load 8000
section RESET load 8000
section SERIAL
section MEMTEST
section VECTORS high 100000

View File

@@ -39,7 +39,7 @@ $(TARGROM): $(TARGET).s19
# Link objects
$(TARGET).s19: $(OBJS)
$(LD) $(LDFLAGS) -o $@ $<
$(LD) $(LDFLAGS) -o $@ $^
# Assemble objects
$(OBJS): $(BUILDDIR)%.o : $(SRCDIR)%.s

View File

@@ -1,118 +0,0 @@
; CHIBI PC-09 Prototype #1 Boot ROM -- Hardware Initialization and Reset Vecs
; Copyright (c) 2024 Amber Zeller, Gale Faraday
; Licensed under MIT
INCLUDE "hardware.inc"
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Hardware Initialization Routines
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
SECTION CODE
;ORG ROM_BASE
RESET
; 8n1 Serial Enable DLAB
lda #UARTF_LCR_WLS | UARTF_LCR_DLAB
sta UART_LCR
; REVIEW: Potential endianness hiccough here
ldd #$0C00 ; Set divisor to 12 (9600 baud)
sta UART_DLM
stb UART_DLL
lda #(UARTF_LCR_WLS) ; 8n1 serial, disable DLAB
sta UART_LCR
lda #(UARTF_MCR_RTS) ; Enable Request-to-Send
sta UART_MCR
lda #'H ; send 'H'
sta UART_BUFR
WAIT
sync ; Wait for interrupts
nop
bra WAIT
;SECTION "Serial"
; Writes a char to the UART in non FIFO mode, preserves A.
; @param b: char to write
OUTCHAR
pshs a ; Preserve A
NOTREADY@
lda UART_LSR ; if LSR.THRE == 1 then write
anda UARTF_LSR_THRE
bne NOTREADY@ ; Loop if UART not ready yet
stb UART_BUFR ; Write char
puls a ; Restore A
rts
; Writes a null terminated string to the UART in non FIFO mode, clobbers A and
; B.
; @param x: null terminated string start address.
OUTSTR
ldb 0,x ; Get the next value from X
cmpb #$00 ; Make sure that we aren't at a terminator
beq END@
leax 1,x ; Increment X for our next char
NOTREADY@ ; Loop point for UART waiting
lda UART_LSR ; Wait for UART to be ready
anda UARTF_LSR_THRE
bne NOTREADY@
stb UART_BUFR ; Actually do our write
bra OUTSTR ; Reset for the next char
END@ ; Jump point for end of routine
rts
;SECTION "Memtest"
; RAM testing routine. Ported to 6809 from 6800, based on source for ROBIT-2 for
; MIKBUG.
RAMTEST
ldx #SRAM_BASE
AGAIN@ ; Store 1 in memory
lda #1 ; Set [X] to 1
sta 0,x
cmpa 0,x ; If failed print out an error indicator
bne ERR@
NEXT@ ; Loop point for next address
asla ; Shift A and [X] left
asl 0,x
cmpa 0,x ; Compare A and [X]
bne ERR@
cmpa #$80 ; Only test up to $80
bne NEXT@ ; Loop if not $80
cmpx #$60FF ; Compare X to end of RAM
beq PASS@ ; Finish if we're at the end
leax 1,x ; Increment X
bra AGAIN@
ERR@ ; Write out error indicator
ldb #'X
jsr OUTCHAR
PASS@ ; Pass test
ldb #'P
jsr OUTCHAR
rts
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Interrupt and Reset Vectors
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
SECTION VECTORS
;ORG VECS_BASE
VECTORS
fdb $0000 ; Reserved
fdb $0000 ; SWI3
fdb $0000 ; SWI2
fdb $0000 ; FIRQ
fdb $0000 ; IRQ
fdb $0000 ; SWI
fdb $0000 ; NMI
fdb RESET ; Reset

42
code/boot/src/memtest.s Normal file
View File

@@ -0,0 +1,42 @@
; CHIBI PC-09 Prototype #1 Boot ROM -- Memory Testing Routines
; Copyright (c) 2024-2025 Amber Zeller, Gale Faraday
; Licensed under MIT
INCLUDE "hardware.inc"
INCLUDE "serial.inc"
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Memory Testing Routines
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
SECTION MEMTEST
; RAM testing routine. Ported to 6809 from 6800, based on source for ROBIT-2 for
; MIKBUG.
RAMTEST
ldx #SRAM_BASE
AGAIN@ ; Store 1 in memory
lda #1 ; Set [X] to 1
sta 0,x
cmpa 0,x ; If failed print out an error indicator
bne ERR@
NEXT@ ; Loop point for next address
asla ; Shift A and [X] left
asl 0,x
cmpa 0,x ; Compare A and [X]
bne ERR@
cmpa #$80 ; Only test up to $80
bne NEXT@ ; Loop if not $80
cmpx #$60FF ; Compare X to end of RAM
beq PASS@ ; Finish if we're at the end
leax 1,x ; Increment X
bra AGAIN@
ERR@ ; Write out error indicator
ldb #'X
jsr OUTCHAR
PASS@ ; Pass test
ldb #'P
jsr OUTCHAR
rts

7
code/boot/src/reset.inc Normal file
View File

@@ -0,0 +1,7 @@
; CHIBI PC-09 Prototype #1 -- Reset Handler Header
; Copyright (c) 2025 Amber Zeller, Gale Faraday
; Licensed under MIT
; vim: ft=asm
RESET IMPORT

35
code/boot/src/reset.s Normal file
View File

@@ -0,0 +1,35 @@
; CHIBI PC-09 Prototype #1 Boot ROM -- Reset Handler
; Copyright (c) 2024-2025 Amber Zeller, Gale Faraday
; Licensed under MIT
INCLUDE "hardware.inc"
INCLUDE "serial.inc"
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Hardware Initialization Routines
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
SECTION RESET
EXPORT RESET
RESET
; 8n1 Serial Enable DLAB
lda #UARTF_LCR_WLS | UARTF_LCR_DLAB
sta UART_LCR
; REVIEW: Potential endianness hiccough here
ldd #$0C00 ; Set divisor to 12 (9600 baud)
sta UART_DLM
stb UART_DLL
lda #(UARTF_LCR_WLS) ; 8n1 serial, disable DLAB
sta UART_LCR
lda #(UARTF_MCR_RTS) ; Enable Request-to-Send
sta UART_MCR
lda #'H ; send 'H'
sta UART_BUFR
WAIT@
sync ; Wait for interrupts
nop
bra WAIT@

8
code/boot/src/serial.inc Normal file
View File

@@ -0,0 +1,8 @@
; CHIBI PC-09 Prototype #1 -- Serial Driver Header
; Copyright (c) 2025 Amber Zeller, Gale Faraday
; Licensed under MIT
; vim: ft=asm
OUTCHAR IMPORT
OUTSTR IMPORT

45
code/boot/src/serial.s Normal file
View File

@@ -0,0 +1,45 @@
; CHIBI PC-09 Prototype #1 Boot ROM -- Serial Driver
; Copyright (c) 2024-2025 Amber Zeller, Gale Faraday
; Licensed under MIT
INCLUDE "hardware.inc"
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Serial UART Driver
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
SECTION SERIAL
EXPORT OUTCHAR
EXPORT OUTSTR
; Writes a char to the UART in non FIFO mode, preserves A.
; @param b: char to write
OUTCHAR
pshs a ; Preserve A
NOTREADY@
lda UART_LSR ; if LSR.THRE == 1 then write
anda UARTF_LSR_THRE
bne NOTREADY@ ; Loop if UART not ready yet
stb UART_BUFR ; Write char
puls a ; Restore A
rts
; Writes a null terminated string to the UART in non FIFO mode, clobbers A and
; B.
; @param x: null terminated string start address.
OUTSTR
ldb 0,x ; Get the next value from X
cmpb #$00 ; Make sure that we aren't at a terminator
beq END@
leax 1,x ; Increment X for our next char
NOTREADY@ ; Loop point for UART waiting
lda UART_LSR ; Wait for UART to be ready
anda UARTF_LSR_THRE
bne NOTREADY@
stb UART_BUFR ; Actually do our write
bra OUTSTR ; Reset for the next char
END@ ; Jump point for end of routine
rts

23
code/boot/src/vecs.s Normal file
View File

@@ -0,0 +1,23 @@
; CHIBI PC-09 Prototype #1 Boot ROM -- Interrupt and Reset Vectors
; Copyright (c) 2024-2025 Amber Zeller, Gale Faraday
; Licensed under MIT
INCLUDE "reset.inc"
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Interrupt and Reset Vectors
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
SECTION VECTORS
VECTORS
fdb $0000 ; Reserved
fdb $0000 ; SWI3
fdb $0000 ; SWI2
fdb $0000 ; FIRQ
fdb $0000 ; IRQ
fdb $0000 ; SWI
fdb $0000 ; NMI
fdb RESET ; Reset