forked from amberisvibin/chibi-pc09
38 lines
1.1 KiB
Markdown
38 lines
1.1 KiB
Markdown
# Motorola 6809 and TI SN74LS612 Timing
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## Motorola 6809 Timing
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Dual phase clock, E and Q. Staggered by half a clock.
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1, 1.5, or 2 mHz. Nanosecond timing will be listed for all 3 speeds.
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* On Q rise, address and R/-W output is valid.
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* On E rise, data output is valid.
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* Time between Q rise and E rise is (approx) minimum 200/130/80ns and max 250/166/125ns.
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* Time between address and R/-W output to data output.
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* On E fall, data input is read. Address and R/-W output become invalid.
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* Data input must be valid for minimum 80/60/40ns before E fall.
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* Output data on Q fall to ensure data input is valid.
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## TI SN74LS612 Timing
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Async
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### Write mode:
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* -Strobe occurs to perform write.
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* -Strobe pulse must be at least 75ns.
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* Data must be valid 75ns before -strobe fall.
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* -CS, R/-W, RS must be low at least 20ns before -strobe fall.
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* -CS, R/-W, RS, Data must be valid at least 20ns after -strobe rise.
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## Interface
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### 6809 Write to SN74LS612
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## Sources
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* Motorola MC6809 Datasheet, undated
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* Motorola MC6809E Datasheet, 1984
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* TI SN54LS610, SN54LS612, SN74LS610 THRU SN74LS613 Datasheet, 1981-1988
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