feat(boot): new baud setup routine

Reviewed-on: amberisvibin/chibi-pc09#1

README.md

@@ -27,4 +27,4 @@ Assembly is in progress.
 
 ## License
 
-This project is licensed under the MIT license. This applies to both the hardware (schematics, bill of materials, pcb layouts) and documentation. This does *not* apply to the datasheets/ directory, the books/ directory or code/assist09/. Those files belong to their respective copyright holders.
+This project is licensed under the MIT license. This applies to both the hardware (schematics, bill of materials, pcb layouts) and documentation. This does *not* apply to the datasheets/ directory or code/assist09/. Those files belong to their respective copyright holders.

code/boot/README.md

@@ -1,31 +1,35 @@
 # Boot Firmware for CHIBI PC-09
 
-TODO: Description of what the firmware does for the PC-09.
+This is the firmware for the CHIBI PC-09. In the future it will provide the
+CHIBI with initialization code, a UART driver, some self test features.
 
 ## Building the Firmware
 
-You will need GNU `make`, and [`asm6809`](https://www.6809.org.uk/asm6809) to
-build the firmware. Obtaining a working copy of `asm6809` could be difficult if
-you aren't on Debian, Ubuntu, or Windows as instructions for building it are not
-given on the `asm6809` website. Functional instructions for building from Git or
-tarball are given here:
+Building the firmware from source requires [LWTOOLS](http://www.lwtools.ca/) for
+building S-Records of the ROM, and `mot2bin` from
+[F9DASM](https://github.com/Arakula/f9dasm) for building binary images. A GNU
+Make makefile is provided for building on Linux.
+
+### Using the Makefile
+
+To generate an S-Record run:
 
 ```sh
-git clone https://www.6809.org.uk/git/asm6809.git
-cd asm6809
-./configure
-make
-sudo make install
+make boot.s19
 ```
 
-From there all you should have to do to generate a `boot.bin` is:
+To generate a binary run:
 
 ```sh
-git clone https://github.com/amberisvibin/chibi-pc09.git
-cd chibi-pc09
 make
 ```
 
+The makefile also can clean up after itself:
+
+```sh
+make clean
+```
+
 ## Firmware Licensing
 
 This firmware like the rest of the CHIBI PC-09 is licensed under the MIT

code/boot/linkscript

@@ -0,0 +1,5 @@
+section RESET load 8000
+section SERIAL
+section MEMTEST
+
+section VECTORS high 100000

code/boot/makefile

@@ -8,26 +8,45 @@
 # Project Defaults & Folders
 # ------------------------------------------------------------------------------
 
-TARGET  := boot.bin
-SRCDIR  := src/
-MAINSRC := $(SRCDIR)boot.s
-SRCS    := $(wildcard $(SRCDIR)*.s)
-INCS    := $(wildcard $(SRCDIR)*.inc)
+TARGET   := boot
+TARGREC  := $(TARGET).s19
+TARGROM  := $(TARGET).bin
+SRCDIR   := src/
+BUILDDIR := build/
+SRCS     := $(wildcard $(SRCDIR)*.s)
+OBJS     := $(patsubst $(SRCDIR)%.s,$(BUILDDIR)%.o,$(SRCS))
+INCS     := $(wildcard $(SRCDIR)*.inc)
 
 # ------------------------------------------------------------------------------
 # Toolchain Definitions
 # ------------------------------------------------------------------------------
 
-AS := asm6809
+AS  := lwasm
+LD  := lwlink
+FIX := objcopy
+
+ASFLAGS := -f obj
+LDFLAGS := -f srec -m map.txt -s linkscript
 
 # ------------------------------------------------------------------------------
 # Rules and Phony Targets
 # ------------------------------------------------------------------------------
 
-all: $(TARGET)
+all: $(TARGROM)
 
-$(TARGET): $(SRCS) $(INCS)
-	$(AS) -o $(TARGET) $(MAINSRC)
+# Fix srec into flashable bin file
+$(TARGROM): $(TARGREC)
+	$(FIX) -I srec -O binary $< $@
+
+# Link objects
+$(TARGREC): $(OBJS)
+	$(LD) $(LDFLAGS) -o $@ $^
+
+# Assemble objects
+$(OBJS): $(BUILDDIR)%.o : $(SRCDIR)%.s
+	-@mkdir -p $(BUILDDIR)
+	$(AS) $(ASFLAGS) -o $@ $<
 
 clean:
-	rm -v $(TARGET)
+	@echo 'Cleaning up intermediary files...'
+	@rm -rv $(TARGROM) $(TARGREC) map.txt $(BUILDDIR)

code/boot/src/boot.s

@@ -1,88 +0,0 @@
-; CHIBI PC-09 Prototype #1 Boot ROM -- Hardware Initialization and Reset Vecs
-; Copyright (c) 2024 Amber Zeller, Gale Faraday
-; Licensed under MIT
-
-  INCLUDE "src/hardware.inc"
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Hardware Initialization Routines
-;;
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-  SECTION "Reset"
-  ORG ROM_BASE
-
-RESET
-  ; 8n1 Serial Enable DLAB
-  lda #(UARTF_LCR_WLS | UARTF_LCR_DLAB)
-  sta UART_LCR
-
-  ; REVIEW: Potential endianness hiccough here
-  ldd #$0C00           ; Set divisor to 12 (9600 baud)
-  sta UART_DLM
-  stb UART_DLL
-
-  lda #(UARTF_LCR_WLS) ; 8n1 serial, disable DLAB
-  sta UART_LCR
-
-  lda #(UARTF_MCR_RTS) ; Enable Request-to-Send
-  sta UART_MCR
-
-  lda 'H               ; send 'H'
-  sta UART_BUFR
-
-WAIT
-  sync                 ; Wait for interrupts
-  nop
-  bra WAIT
-
-  SECTION "Serial"
-
-; Writes a char to the UART in non FIFO mode, preserves A.
-; @param b: char to write
-OUTCHAR
-  pshs a               ; Preserve A
-1
-  lda UART_LSR         ; if LSR.THRE == 1 then write
-  anda UARTF_LSR_THRE
-  bne 1B               ; Loop if UART not ready yet
-  stb UART_BUFR        ; Write char
-  puls a               ; Restore A
-  rts
-
-; Writes a null terminated string to the UART in non FIFO mode, clobbers A and
-; B.
-; @param x: null terminated string start address.
-OUTSTR
-  ldb x                ; Get the next value from X
-  cmpb #$00            ; Make sure that mother is non-null
-  beq 2F
-  leax 1,x             ; Increment X for our next char
-1                      ; Loop point for UART waiting
-  lda UART_LSR         ; Wait for UART to be ready
-  anda UARTF_LSR_THRE
-  bne 1B
-  stb UART_BUFR        ; Actually do our write
-  bra OUTSTR           ; Reset for the next char
-2                      ; Jump point for end of routine
-  rts
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Interrupt and Reset Vectors
-;;
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-  SECTION "Vectors"
-  ORG VECS_BASE
-
-VECTORS
-  fdb $0000 ; Reserved
-  fdb $0000 ; SWI3
-  fdb $0000 ; SWI2
-  fdb $0000 ; FIRQ
-  fdb $0000 ; IRQ
-  fdb $0000 ; SWI
-  fdb $0000 ; NMI
-  fdb RESET ; Reset

code/boot/src/hardware.inc

@@ -1,7 +1,9 @@
 ; CHIBI PC-09 Hardware Definitions
-; Copyright (c) 2024 Amber Zeller, Gale Faraday
+; Copyright (c) 2024-2025 Amber Zeller, Gale Faraday
 ; Licensed under MIT
 
+; vim: ft=asm
+
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;;
 ;; Hardware Base Addresses
@@ -13,6 +15,16 @@ UART_BASE EQU $7F00 ; UART Base Address
 ROM_BASE  EQU $8000 ; ROM Base Address and Entry Point
 VECS_BASE EQU $FFF0 ; Vectors Base Address
 
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Stack Base Address and Size Information
+;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+STACK_BOTTOM EQU $0100 ; Bottom address of system stack
+STACK_DEPTH  EQU $FF   ; System stack's depth
+STACK_TOP    EQU STACK_BOTTOM+STACK_DEPTH ; Top address of system stack
+
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;;
 ;; UART Registers and Flags
@@ -20,23 +32,23 @@ VECS_BASE EQU $FFF0 ; Vectors Base Address
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 ; When UARTF_LCR_DLAB = 0:
-UART_BUFR EQU UART_BASE    ; TX/RX Buffer (Read for RX, Write for TX)
-UART_RBR EQU UART_BASE     ; RX Buffer Register
-UART_THR EQU UART_BASE     ; TX Holding Register
-UART_IER EQU UART_BASE + 1 ; Interrupt Enable Register
+UART_BUFR EQU UART_BASE  ; TX/RX Buffer (Read for RX, Write for TX)
+UART_RBR EQU UART_BASE   ; RX Buffer Register
+UART_THR EQU UART_BASE   ; TX Holding Register
+UART_IER EQU UART_BASE+1 ; Interrupt Enable Register
 
 ; When UARTF_LCR_DLAB = 1:
-UART_DLL EQU UART_BASE     ; Divisor Latch (LSB)
-UART_DLM EQU UART_BASE + 1 ; Divisor Latch (MSB)
+UART_DLL EQU UART_BASE   ; Divisor Latch (LSB)
+UART_DLM EQU UART_BASE+1 ; Divisor Latch (MSB)
 
 ; Independent of DLAB:
-UART_IIR EQU UART_BASE + 2 ; Interrupt Ident Register (Upon Read)
-UART_FCR EQU UART_BASE + 2 ; FIFO Control Register (Upon Write)
-UART_LCR EQU UART_BASE + 3 ; Line Control Register
-UART_MCR EQU UART_BASE + 4 ; MODEM Control Register
-UART_LSR EQU UART_BASE + 5 ; Line Status Register
-UART_MSR EQU UART_BASE + 6 ; MODEM Status Register
-UART_SCR EQU UART_BASE + 7 ; Scratch Register (Not for control just spare RAM)
+UART_IIR EQU UART_BASE+2 ; Interrupt Ident Register (Upon Read)
+UART_FCR EQU UART_BASE+2 ; FIFO Control Register (Upon Write)
+UART_LCR EQU UART_BASE+3 ; Line Control Register
+UART_MCR EQU UART_BASE+4 ; MODEM Control Register
+UART_LSR EQU UART_BASE+5 ; Line Status Register
+UART_MSR EQU UART_BASE+6 ; MODEM Status Register
+UART_SCR EQU UART_BASE+7 ; Scratch Register (Not for control just spare RAM)
 
 ; UART Flags for Interrupt Enable Register:
 UARTF_IER_ERBFI EQU %10000000 ; Enable Received Data Available Interrupt
@@ -93,4 +105,3 @@ UARTF_MSR_DSR  EQU %00000100 ; Data Set Ready
 UARTF_MSR_RI   EQU %00000010 ; Ring Indicator
 UARTF_MSR_DCD  EQU %00000001 ; Data Carrier Detect
 
-; vim: ft=asm

code/boot/src/memtest.s

@@ -0,0 +1,42 @@
+; CHIBI PC-09 Prototype #1 Boot ROM -- Memory Testing Routines
+; Copyright (c) 2024-2025 Amber Zeller, Gale Faraday
+; Licensed under MIT
+
+  INCLUDE "hardware.inc"
+  INCLUDE "serial.inc"
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Memory Testing Routines
+;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+  SECTION MEMTEST
+
+; RAM testing routine. Ported to 6809 from 6800, based on source for ROBIT-2 for
+; MIKBUG.
+RAMTEST
+  ldx #SRAM_BASE
+AGAIN@                 ; Store 1 in memory
+  lda #1               ; Set [X] to 1
+  sta 0,x
+  cmpa 0,x             ; If failed print out an error indicator
+  bne ERR@
+NEXT@                  ; Loop point for next address
+  asla                 ; Shift A and [X] left
+  asl 0,x
+  cmpa 0,x             ; Compare A and [X]
+  bne ERR@
+  cmpa #$80            ; Only test up to $80
+  bne NEXT@            ; Loop if not $80
+  cmpx #$60FF          ; Compare X to end of RAM
+  beq PASS@            ; Finish if we're at the end
+  leax 1,x             ; Increment X
+  bra AGAIN@
+ERR@                   ; Write out error indicator
+  ldb #'X
+  jsr OUTCHAR
+PASS@                  ; Pass test
+  ldb #'P
+  jsr OUTCHAR
+  rts

code/boot/src/reset.inc

@@ -0,0 +1,7 @@
+; CHIBI PC-09 Prototype #1 -- Reset Handler Header
+; Copyright (c) 2025 Amber Zeller, Gale Faraday
+; Licensed under MIT
+
+; vim: ft=asm
+
+RESET IMPORT

code/boot/src/reset.s

@@ -0,0 +1,49 @@
+; CHIBI PC-09 Prototype #1 Boot ROM -- Reset Handler
+; Copyright (c) 2024-2025 Amber Zeller, Gale Faraday
+; Licensed under MIT
+
+  INCLUDE "hardware.inc"
+  INCLUDE "serial.inc"
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Hardware Initialization Routines
+;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+  SECTION RESET
+
+  EXPORT RESET
+
+RESET
+
+CLRSTACK
+  ; Initialize the system stack
+  lda #$00           ; Initialize A & X to zero out the stack
+  ldx #$0000
+NEXT@
+  sta STACK_BOTTOM,x ; Write a zero and progress to the next byte
+  leax 1,x
+  cmpx #STACK_DEPTH  ; See if we're at the top of the stack yet
+  blo NEXT@          ; Loop if we aren't at the end yet
+  lds STACK_TOP      ; Set S to top of newly cleared stack
+
+SERINIT
+  ; 8n1 Serial Enable DLAB
+  lda #UARTF_LCR_WLS|UARTF_LCR_DLAB
+  sta UART_LCR
+  ; REVIEW: Potential endianness hiccough here
+  ldd #$0C00           ; Set divisor to 12 (9600 baud)
+  sta UART_DLM
+  stb UART_DLL
+  lda #(UARTF_LCR_WLS) ; 8n1 serial, disable DLAB
+  sta UART_LCR
+  lda #(UARTF_MCR_RTS) ; Enable Request-to-Send
+  sta UART_MCR
+  lda #'H               ; send 'H'
+  sta UART_THR
+
+WAIT
+  sync                 ; Wait for interrupts
+  nop
+  bra WAIT

code/boot/src/serial.inc

@@ -0,0 +1,8 @@
+; CHIBI PC-09 Prototype #1 -- Serial Driver Header
+; Copyright (c) 2025 Amber Zeller, Gale Faraday
+; Licensed under MIT
+
+; vim: ft=asm
+
+OUTCHAR IMPORT
+OUTSTR IMPORT

code/boot/src/serial.s

@@ -0,0 +1,61 @@
+; CHIBI PC-09 Prototype #1 Boot ROM -- Serial Driver
+; Copyright (c) 2024-2025 Amber Zeller, Gale Faraday
+; Licensed under MIT
+
+  INCLUDE "hardware.inc"
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Serial UART Driver
+;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+  SECTION SERIAL
+
+  EXPORT SETBAUD
+  EXPORT OUTCHAR
+  EXPORT OUTSTR
+
+; Initializes the UART.
+; @param d: new divisor
+SETBAUD
+  pshs a              ; Preserve A
+  lda UART_LCR        ; Set only the DLAB bit
+  ora #UARTF_LCR_DLAB
+  sta UART_LCR
+  puls a
+  sta UART_DLM        ; Store new divisor
+  stb UART_DLL
+  lda UART_LCR        ; Reset DLAB
+  anda #$FE
+  sta UART_LCR
+  rts
+
+; Writes a char to the UART in non FIFO mode, preserves A.
+; @param b: char to write
+OUTCHAR
+  pshs a               ; Preserve A
+NOTREADY@
+  lda UART_LSR         ; if LSR.THRE == 1 then write
+  anda UARTF_LSR_THRE
+  bne NOTREADY@        ; Loop if UART not ready yet
+  stb UART_THR         ; Write char
+  puls a               ; Restore A
+  rts
+
+; Writes a null terminated string to the UART in non FIFO mode, clobbers A and
+; B.
+; @param x: null terminated string start address.
+OUTSTR
+  ldb 0,x              ; Get the next value from X
+  cmpb #$00            ; Make sure that we aren't at a terminator
+  beq END@
+  leax 1,x             ; Increment X for our next char
+NOTREADY@              ; Loop point for UART waiting
+  lda UART_LSR         ; Wait for UART to be ready
+  anda UARTF_LSR_THRE
+  bne NOTREADY@
+  stb UART_THR         ; Actually do our write
+  bra OUTSTR           ; Reset for the next char
+END@                   ; Jump point for end of routine
+  rts

code/boot/src/vecs.s

@@ -0,0 +1,23 @@
+; CHIBI PC-09 Prototype #1 Boot ROM -- Interrupt and Reset Vectors
+; Copyright (c) 2024-2025 Amber Zeller, Gale Faraday
+; Licensed under MIT
+
+  INCLUDE "reset.inc"
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Interrupt and Reset Vectors
+;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+  SECTION VECTORS
+
+VECTORS
+  fdb $0000 ; Reserved
+  fdb $0000 ; SWI3
+  fdb $0000 ; SWI2
+  fdb $0000 ; FIRQ
+  fdb $0000 ; IRQ
+  fdb $0000 ; SWI
+  fdb $0000 ; NMI
+  fdb RESET ; Reset

docs/74ls612.txt

@@ -1,6 +0,0 @@
-TTL devices can handle CMOS input. HD6309 -> 74LS612
-CMOS devices may or may not handle TTL input. 74LS612 -> peripherals
-
-62256 SRAM, 28C256 EEPROM, 16550 UART all handle TTL input.
-82C42 lists it's outputs as TTL compatible, but says nothing for inputs.
-Must ensure all peripherals are rated for TTL input.

docs/README.md

@@ -3,7 +3,6 @@
 File descriptions:
 
 - links.txt contains useful links i would like to keep
-- 6809-sn74ls612_timing.md contains notes on the mmu and cpu interface
 - tech-spec.md contains basic info on layout of system (outdated)
 - timing.html contains info on vga timing pulled from https://martin.hinner.info/vga/timing.html
 - vga_ram.txt contains notes on ram size for the vga card

pcb/.gitignore

@@ -0,0 +1 @@
+fp-info-cache

pcb/prototype-1/v1.1/prototype-1.kicad_prl

@@ -1,6 +1,6 @@
 {
   "board": {
-    "active_layer": 5,
+    "active_layer": 0,
     "active_layer_preset": "",
     "auto_track_width": true,
     "hidden_netclasses": [],
@@ -51,7 +51,7 @@
       "shapes"
     ],
     "visible_layers": "ffffffff_ffffffff_ffffffff_ffffffff",
-    "zone_display_mode": 0
+    "zone_display_mode": 1
   },
   "git": {
     "repo_type": "",
@@ -59,7 +59,7 @@
     "ssh_key": ""
   },
   "meta": {
-    "filename": "prototype-1(v1.1).kicad_prl",
+    "filename": "prototype-1.kicad_prl",
     "version": 5
   },
   "net_inspector_panel": {