forked from amberisvibin/chibi-pc09
start working on boot code, move things around
This commit is contained in:
@@ -21,4 +21,4 @@ Prototype 1 is currently in progress. It will be a much simpler system. It will
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## License
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This project is licensed under the MIT license. This applies to both the hardware (schematics, bill of materials, pcb layouts) and documentation. This does *not* apply to the datasheets/ directory, the code/books/ directory or code/assist09.asm. Those files belong to their respective copyright holders.
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This project is licensed under the MIT license. This applies to both the hardware (schematics, bill of materials, pcb layouts) and documentation. This does *not* apply to the datasheets/ directory, the books/ directory or code/assist09/assist09.asm. Those files belong to their respective copyright holders.
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BIN
books/manual.pdf
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BIN
books/manual.pdf
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Binary file not shown.
@@ -1,5 +1,13 @@
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# Code
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## assist09/
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assist09.asm is the original motorola version, and relies on the as9 assembler found [here](http://home.hccnet.nl/a.w.m.van.der.horst/m6809.html).
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assemble.sh will assemble assist09.asm to an s19 file and use gnu binutils objcopy to turn that into a bin file.
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## boot/
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the boot code for prototype 1, uses the lwtools assembler.
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assemble.sh will assemble boot.s to an s19 file and use gnu binutils objcopy to turn that into a bin file.
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3
code/boot/assemble.sh
Executable file
3
code/boot/assemble.sh
Executable file
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lwasm --format=srec --output=boot.s19 boot.s
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objcopy --input-target=srec --output-target=binary boot.s19 boot.bin
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#mot2bin -out boot.bin boot.s19
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BIN
code/boot/boot.bin
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BIN
code/boot/boot.bin
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Binary file not shown.
3
code/boot/boot.ld
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3
code/boot/boot.ld
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section code load 8000
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pad FFFF
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section vectors load FFF0
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44
code/boot/boot.s
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44
code/boot/boot.s
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; CHIBI PC-09 Prototype #1 Boot ROM
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; (Copyright (c) 2024 Amber Zeller
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; UART registers
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UART = $7F00
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; When DLAB = 0
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BUFR = UART ; TX/RX Buffer (Read for RX, Write for TX)
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IER = UART + 1 ; Interrupt Enable Register
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IIR = UART + 1 ; Interrupt Enable Register (Upon Read)
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; When DLAB = 1
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DLL = UART ; Divisor Latch (LSB)
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DLM = UART + 1 ; Divisor Latch (MSB)
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FCR = UART + 2 ; FIFO Control Register (Upon Write)
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LCR = UART + 3 ; Line Control Register
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MCR = UART + 4 ; MODEM Control Register
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LSR = UART + 5 ; Line Status Register
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MSR = UART + 6 ; MODEM Status Register
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SCR = UART + 7 ; Scratch Register (Not for control just spare RAM)
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; SECTION code
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org $8000
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RESET:
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sta $cc
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jmp RESET
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fdb RESET
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; ENDSECTION
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; SECTION vectors
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org $FFF0
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; Reset/Interrupt Vectors
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fdb $0000 ; Reserved
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fdb $0000 ; SWI3
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fdb $0000 ; SWI2
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fdb $0000 ; FIRQ
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fdb $0000 ; IRQ
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fdb $0000 ; SWI
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fdb $0000 ; NMI
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fdb RESET ; Reset
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; ENDSECTION
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5
code/boot/boot.s19
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5
code/boot/boot.s19
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@@ -0,0 +1,5 @@
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S01800005B6C77746F6F6C7320342E32335D20626F6F742E73BF
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S10A800097CC7E8000800094
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S113FFF0000000000000000000000000000080007D
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S5030002FA
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S9030000FC
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10
code/boot/devenvironment.md
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10
code/boot/devenvironment.md
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# Dev environment
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USE:
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- [lwtools](http://www.lwtools.ca/)
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- [f9dasm](https://github.com/Arakula/f9dasm)
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lwtools uses lwasm
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f9dasm uses f9dasm
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@@ -1,15 +1,15 @@
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# 6309 Board Prototype #1 Specs
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HD63C09 CPU @ 3MHz
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HM62256BLP-7 SRAM
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AT28C256-15 EEPROM
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ST16C550 UART @ 1.8342MHz (XO due to lack of 22pf 1.8432MHz XTALs)
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AS6C62256-55 SRAM (32KB)
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SST39SF010A-70 FLASH (32KB Used)
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PC16550 UART @ 1.8342MHz
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## Memory Map
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| Device | Location |
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|--------|-----------|
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| EEPROM | 8000-FFFF |
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| FLASH | 8000-FFFF |
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| UART | 7F00-7FFF |
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| SRAM | 0000-7EFF |
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@@ -17,6 +17,6 @@ ST16C550 UART @ 1.8342MHz (XO due to lack of 22pf 1.8432MHz XTALs)
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| A15 | A14-A9 | A8 | Chip |
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|-----|--------|----|--------|
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| H | x | x | EEPROM |
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| H | x | x | FLASH |
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| L | x | L | SRAM |
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| L | H | H | UART |
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