108 lines
4.2 KiB
PHP
108 lines
4.2 KiB
PHP
; CHIBI PC-09 Hardware Definitions
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; Copyright (c) 2024-2025 Amber Zeller, Gale Faraday
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; Licensed under MIT
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; vim: ft=asm
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; Hardware Base Addresses
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;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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SRAM_BASE EQU $0000 ; SRAM Base Address
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UART_BASE EQU $7F00 ; UART Base Address
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ROM_BASE EQU $8000 ; ROM Base Address and Entry Point
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VECS_BASE EQU $FFF0 ; Vectors Base Address
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; Stack Base Address and Size Information
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;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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STACK_BOTTOM EQU $0100 ; Bottom address of system stack
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STACK_DEPTH EQU $FF ; System stack's depth
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STACK_TOP EQU STACK_BOTTOM+STACK_DEPTH ; Top address of system stack
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; UART Registers and Flags
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;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; When UARTF_LCR_DLAB = 0:
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UART_BUFR EQU UART_BASE ; TX/RX Buffer (Read for RX, Write for TX)
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UART_RBR EQU UART_BASE ; RX Buffer Register
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UART_THR EQU UART_BASE ; TX Holding Register
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UART_IER EQU UART_BASE+1 ; Interrupt Enable Register
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; When UARTF_LCR_DLAB = 1:
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UART_DLL EQU UART_BASE ; Divisor Latch (LSB)
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UART_DLM EQU UART_BASE+1 ; Divisor Latch (MSB)
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; Independent of DLAB:
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UART_IIR EQU UART_BASE+2 ; Interrupt Ident Register (Upon Read)
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UART_FCR EQU UART_BASE+2 ; FIFO Control Register (Upon Write)
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UART_LCR EQU UART_BASE+3 ; Line Control Register
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UART_MCR EQU UART_BASE+4 ; MODEM Control Register
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UART_LSR EQU UART_BASE+5 ; Line Status Register
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UART_MSR EQU UART_BASE+6 ; MODEM Status Register
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UART_SCR EQU UART_BASE+7 ; Scratch Register (Not for control just spare RAM)
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; UART Flags for Interrupt Enable Register:
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UARTF_IER_ERBFI EQU %00000001 ; Enable Received Data Available Interrupt
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UARTF_IER_ETBEI EQU %00000010 ; Enable Transmitter Holding Register Empty Interrupt
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UARTF_IER_ELSI EQU %00000100 ; Enable Receiver Line Status Interrupt
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UARTF_IER_EDSSI EQU %00001000 ; Enable MODEM Status Interrupt
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; UART Flags for FIFO Control Register:
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UARTF_FCR_FE EQU %00000001 ; FIFO Enabled
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UARTF_FCR_RFR EQU %00000010 ; RCVR FIFO Reset
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UARTF_FCR_XFR EQU %00000100 ; XMIT FIFO Reset
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UARTF_FCR_DMS EQU %00001000 ; DMA Mode Select
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UARTF_FCR_RTL EQU %01000000 ; RCVR Trigger (LSB)
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UARTF_FCR_RTM EQU %10000000 ; RCVR Trigger (MSB)
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; UART Flags for Interrupt Ident Register:
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UARTF_IIR_INP EQU %00000001 ; Reset if Interrupt Pending; 'INP' = Interrupt Not Pending
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UARTF_IIR_IIDM EQU %00001110 ; Interrupt ID Mask
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UARTF_IIR_FEM EQU %11000000 ; FIFOs Enabled Mask
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; UART Flags for Line Control Register:
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UARTF_LCR_WLS EQU %00000011 ; Word Length Select Bits
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UARTF_LCR_STB EQU %00000100 ; Stop Bits
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UARTF_LCR_PEN EQU %00001000 ; Parity Enable
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UARTF_LCR_EPS EQU %00010000 ; Even Parity Select
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UARTF_LCR_SPR EQU %00100000 ; Stick Parity
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UARTF_LCR_BRK EQU %01000000 ; Set Break
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UARTF_LCR_DLAB EQU %10000000 ; Divisor Latch Access Bit
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; UART Flags for MODEM Control Register:
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UARTF_MCR_DTR EQU %00000001 ; Data Terminal Ready
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UARTF_MCR_RTS EQU %00000010 ; Enabling Request to Send
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UARTF_MCR_OUT1 EQU %00000100 ; Out 1
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UARTF_MCR_OUT2 EQU %00001000 ; Out 2
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UARTF_MCR_LOOP EQU %00010000 ; Loop
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; UART Flags for Line Status Register:
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UARTF_LSR_DR EQU %00000001 ; Data Ready
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UARTF_LSR_OE EQU %00000010 ; Overrun Error
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UARTF_LSR_PE EQU %00000100 ; Parity Error
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UARTF_LSR_FE EQU %00001000 ; Framing Error
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UARTF_LSR_BI EQU %00010000 ; Break Interrupt
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UARTF_LSR_THRE EQU %00100000 ; Transmitter Holding Register
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UARTF_LSR_TEMT EQU %01000000 ; Transmitter Empty
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UARTF_LSR_FIFO EQU %10000000 ; Error in RCVR FIFO
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; UART Flags for MODEM Status Register:
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UARTF_MSR_DCTS EQU %00000001 ; Delta Clear to Send
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UARTF_MSR_DDSR EQU %00000010 ; Delta Data Set Ready
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UARTF_MSR_TERI EQU %00000100 ; Trailing Edge Ring Indicator
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UARTF_MSR_DDCD EQU %00001000 ; Delta Data Carrier Detect
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UARTF_MSR_CTS EQU %00010000 ; Clear To Send
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UARTF_MSR_DSR EQU %00100000 ; Data Set Ready
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UARTF_MSR_RI EQU %01000000 ; Ring Indicator
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UARTF_MSR_DCD EQU %10000000 ; Data Carrier Detect
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