Populate repository from old progress; massive cleanup and fixes
This commit is contained in:
22
.editorconfig
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22
.editorconfig
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@@ -0,0 +1,22 @@
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# Editorconfig for CHIBI PC-09 Firmware
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||||
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||||
root = true
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[*]
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end_of_line = lf
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charset = utf-8
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trim_trailing_whitespace = true
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insert_final_newline = true
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[*.{s,inc}]
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indent_style = space
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indent_size = 2
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[*.md]
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indent_style = space
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indent_size = 2
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max_line_length = 80
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[makefile]
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indent_style = tab
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indent_size = 4
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11
.gitignore
vendored
Normal file
11
.gitignore
vendored
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@@ -0,0 +1,11 @@
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# Gitignore for CHIBI PC-09 Firmware
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# Ignore product files
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*.o
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*.bin
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*.s19
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build/
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map.txt
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# Build system generated files
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src/version.s
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42
README.md
42
README.md
@@ -1,3 +1,41 @@
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# chibi-firmware
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# CHIBI PC-09 BIOS
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CHIBI PC-09 BIOS and BUZBEE monitor
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This is the firmware for the CHIBI PC-09. In the future it will provide the
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CHIBI with initialization code, a UART driver, some self test features, as well
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as the "BUZBEE" machine language monitor.
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## Building the Firmware
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Building the firmware from source requires [LWTOOLS](http://www.lwtools.ca/) for
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building S-Records of the ROM. GNU Binutils' `objcopy` is used to translate
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S-Records into ROM images. A GNU Make makefile is provided.
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### Using the Makefile
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To generate an S-Record run:
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```sh
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make generate
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make boot.s19
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```
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To generate a binary run:
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```sh
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make generate
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make
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```
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The makefile also can clean up after itself (this will remove generated files as
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well):
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```sh
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make clean
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```
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## Firmware Licensing
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This firmware like the rest of the CHIBI PC-09 is licensed under the MIT
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license.
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CHIBI PC-09 BIOS (c) Amber Zeller, Gale Faraday
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33
genver.sh
Executable file
33
genver.sh
Executable file
@@ -0,0 +1,33 @@
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#!/usr/bin/env sh
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# Script to generate version information
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# Current git tag
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TAG="$(git describe --always --dirty --tags)"
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DATE="$(date)"
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# Output filename
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OUTFILE='src/version.s'
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sed -e "s/<TAG>/$TAG/g" -e "s/<DATE>/$DATE/g" <<EOF > "$OUTFILE"
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; CHIBI PC-09 Prototype #1 Boot ROM -- Version Information
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; Copyright (c) 2024-2025 Amber Zeller, Gale Faraday
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; Licensed under MIT
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; This file generated by genver.sh
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; Boot ROM Version & Build Information
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;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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SECTION VERSION
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EXPORT VERMSG
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VERMSG
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fcc "CHIBI PC-09 BOOT ROM <TAG>"
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fcb \$0A
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fcn "BUILT <DATE>"
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EOF
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6
linkscript
Normal file
6
linkscript
Normal file
@@ -0,0 +1,6 @@
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section RESET load 8000
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section SERIAL
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section MEMTEST
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section VECTORS high 100000
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section VERSION high
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59
makefile
Normal file
59
makefile
Normal file
@@ -0,0 +1,59 @@
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# Makefile for CHIBI PC-09 Firmware
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.PHONY: generate all clean
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.IGNORE: clean
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.DEFAULT_GOAL := all
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# ------------------------------------------------------------------------------
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# Project Defaults & Folders
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# ------------------------------------------------------------------------------
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TARGET := boot
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TARGREC := $(TARGET).s19
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TARGROM := $(TARGET).bin
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SRCDIR := src/
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BUILDDIR := build/
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GENS := $(SRCDIR)version.s
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SRCS := $(wildcard $(SRCDIR)*.s)
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OBJS := $(patsubst $(SRCDIR)%.s,$(BUILDDIR)%.o,$(SRCS))
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INCS := $(wildcard $(SRCDIR)*.inc)
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# ------------------------------------------------------------------------------
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# Toolchain Definitions
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# ------------------------------------------------------------------------------
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AS := lwasm
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LD := lwlink
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FIX := objcopy
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ASFLAGS := -f obj
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LDFLAGS := -f srec -m map.txt -s linkscript
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# ------------------------------------------------------------------------------
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# Rules and Phony Targets
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# ------------------------------------------------------------------------------
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all: $(TARGROM)
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# Fix srec into flashable bin file
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$(TARGROM): $(TARGREC)
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$(FIX) -I srec -O binary $< $@
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# Link objects
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$(TARGREC): $(OBJS)
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$(LD) $(LDFLAGS) -o $@ $^
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# Assemble objects
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$(OBJS): $(BUILDDIR)%.o : $(SRCDIR)%.s
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-@mkdir -p $(BUILDDIR)
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$(AS) $(ASFLAGS) -o $@ $<
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generate: $(GENS)
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$(GENS):
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./genver.sh
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clean:
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@echo 'Cleaning up intermediary files...'
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@rm -rv $(TARGROM) $(TARGREC) map.txt $(BUILDDIR)
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@rm -rv $(GENS)
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107
src/hardware.inc
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107
src/hardware.inc
Normal file
@@ -0,0 +1,107 @@
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; CHIBI PC-09 Hardware Definitions
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; Copyright (c) 2024-2025 Amber Zeller, Gale Faraday
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; Licensed under MIT
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; vim: ft=asm
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; Hardware Base Addresses
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;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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SRAM_BASE EQU $0000 ; SRAM Base Address
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UART_BASE EQU $7F00 ; UART Base Address
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ROM_BASE EQU $8000 ; ROM Base Address and Entry Point
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VECS_BASE EQU $FFF0 ; Vectors Base Address
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; Stack Base Address and Size Information
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;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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STACK_BOTTOM EQU $0100 ; Bottom address of system stack
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STACK_DEPTH EQU $FF ; System stack's depth
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STACK_TOP EQU STACK_BOTTOM+STACK_DEPTH ; Top address of system stack
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; UART Registers and Flags
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;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; When UARTF_LCR_DLAB = 0:
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UART_BUFR EQU UART_BASE ; TX/RX Buffer (Read for RX, Write for TX)
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UART_RBR EQU UART_BASE ; RX Buffer Register
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UART_THR EQU UART_BASE ; TX Holding Register
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UART_IER EQU UART_BASE+1 ; Interrupt Enable Register
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; When UARTF_LCR_DLAB = 1:
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UART_DLL EQU UART_BASE ; Divisor Latch (LSB)
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UART_DLM EQU UART_BASE+1 ; Divisor Latch (MSB)
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; Independent of DLAB:
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UART_IIR EQU UART_BASE+2 ; Interrupt Ident Register (Upon Read)
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UART_FCR EQU UART_BASE+2 ; FIFO Control Register (Upon Write)
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UART_LCR EQU UART_BASE+3 ; Line Control Register
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UART_MCR EQU UART_BASE+4 ; MODEM Control Register
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UART_LSR EQU UART_BASE+5 ; Line Status Register
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UART_MSR EQU UART_BASE+6 ; MODEM Status Register
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UART_SCR EQU UART_BASE+7 ; Scratch Register (Not for control just spare RAM)
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; UART Flags for Interrupt Enable Register:
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UARTF_IER_ERBFI EQU %00000001 ; Enable Received Data Available Interrupt
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UARTF_IER_ETBEI EQU %00000010 ; Enable Transmitter Holding Register Empty Interrupt
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UARTF_IER_ELSI EQU %00000100 ; Enable Receiver Line Status Interrupt
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UARTF_IER_EDSSI EQU %00001000 ; Enable MODEM Status Interrupt
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; UART Flags for FIFO Control Register:
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UARTF_FCR_FE EQU %00000001 ; FIFO Enabled
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UARTF_FCR_RFR EQU %00000010 ; RCVR FIFO Reset
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UARTF_FCR_XFR EQU %00000100 ; XMIT FIFO Reset
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UARTF_FCR_DMS EQU %00001000 ; DMA Mode Select
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UARTF_FCR_RTL EQU %01000000 ; RCVR Trigger (LSB)
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UARTF_FCR_RTM EQU %10000000 ; RCVR Trigger (MSB)
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; UART Flags for Interrupt Ident Register:
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UARTF_IIR_INP EQU %00000001 ; Reset if Interrupt Pending; 'INP' = Interrupt Not Pending
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UARTF_IIR_IIDM EQU %00001110 ; Interrupt ID Mask
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UARTF_IIR_FEM EQU %11000000 ; FIFOs Enabled Mask
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; UART Flags for Line Control Register:
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UARTF_LCR_WLS EQU %00000011 ; Word Length Select Bits
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UARTF_LCR_STB EQU %00000100 ; Stop Bits
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UARTF_LCR_PEN EQU %00001000 ; Parity Enable
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UARTF_LCR_EPS EQU %00010000 ; Even Parity Select
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UARTF_LCR_SPR EQU %00100000 ; Stick Parity
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UARTF_LCR_BRK EQU %01000000 ; Set Break
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UARTF_LCR_DLAB EQU %10000000 ; Divisor Latch Access Bit
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; UART Flags for MODEM Control Register:
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UARTF_MCR_DTR EQU %00000001 ; Data Terminal Ready
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UARTF_MCR_RTS EQU %00000010 ; Enabling Request to Send
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UARTF_MCR_OUT1 EQU %00000100 ; Out 1
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UARTF_MCR_OUT2 EQU %00001000 ; Out 2
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UARTF_MCR_LOOP EQU %00010000 ; Loop
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; UART Flags for Line Status Register:
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UARTF_LSR_DR EQU %00000001 ; Data Ready
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UARTF_LSR_OE EQU %00000010 ; Overrun Error
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UARTF_LSR_PE EQU %00000100 ; Parity Error
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UARTF_LSR_FE EQU %00001000 ; Framing Error
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UARTF_LSR_BI EQU %00010000 ; Break Interrupt
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UARTF_LSR_THRE EQU %00100000 ; Transmitter Holding Register
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UARTF_LSR_TEMT EQU %01000000 ; Transmitter Empty
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UARTF_LSR_FIFO EQU %10000000 ; Error in RCVR FIFO
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; UART Flags for MODEM Status Register:
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UARTF_MSR_DCTS EQU %00000001 ; Delta Clear to Send
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UARTF_MSR_DDSR EQU %00000010 ; Delta Data Set Ready
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UARTF_MSR_TERI EQU %00000100 ; Trailing Edge Ring Indicator
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UARTF_MSR_DDCD EQU %00001000 ; Delta Data Carrier Detect
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UARTF_MSR_CTS EQU %00010000 ; Clear To Send
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UARTF_MSR_DSR EQU %00100000 ; Data Set Ready
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UARTF_MSR_RI EQU %01000000 ; Ring Indicator
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UARTF_MSR_DCD EQU %10000000 ; Data Carrier Detect
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|
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7
src/memtest.inc
Normal file
7
src/memtest.inc
Normal file
@@ -0,0 +1,7 @@
|
||||
; CHIBI PC-09 Prototype #1 -- Memory Testing Routines Header
|
||||
; Copyright (c) 2025 Amber Zeller, Gale Faraday
|
||||
; Licensed under MIT
|
||||
|
||||
; vim: ft=asm
|
||||
|
||||
RAMTEST IMPORT
|
||||
44
src/memtest.s
Normal file
44
src/memtest.s
Normal file
@@ -0,0 +1,44 @@
|
||||
; CHIBI PC-09 Prototype #1 Boot ROM -- Memory Testing Routines
|
||||
; Copyright (c) 2024-2025 Amber Zeller, Gale Faraday
|
||||
; Licensed under MIT
|
||||
|
||||
INCLUDE "hardware.inc"
|
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INCLUDE "serial.inc"
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Memory Testing Routines
|
||||
;;
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
|
||||
SECTION MEMTEST
|
||||
|
||||
EXPORT RAMTEST
|
||||
|
||||
; RAM testing routine. Ported to 6809 from 6800, based on source for ROBIT-2 for
|
||||
; MIKBUG.
|
||||
RAMTEST
|
||||
ldx #SRAM_BASE
|
||||
AGAIN@ ; Store 1 in memory
|
||||
lda #1 ; Set [X] to 1
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||||
sta 0,x
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||||
cmpa 0,x ; If failed print out an error indicator
|
||||
bne ERR@
|
||||
NEXT@ ; Loop point for next address
|
||||
asla ; Shift A and [X] left
|
||||
asl 0,x
|
||||
cmpa 0,x ; Compare A and [X]
|
||||
bne ERR@
|
||||
cmpa #$80 ; Only test up to $80
|
||||
bne NEXT@ ; Loop if not $80
|
||||
cmpx #$60FF ; Compare X to end of RAM
|
||||
beq PASS@ ; Finish if we're at the end
|
||||
leax 1,x ; Increment X
|
||||
bra AGAIN@
|
||||
ERR@ ; Write out error indicator
|
||||
ldb #'X
|
||||
jsr POUTCHAR
|
||||
PASS@ ; Pass test
|
||||
ldb #'P
|
||||
jsr POUTCHAR
|
||||
rts
|
||||
7
src/reset.inc
Normal file
7
src/reset.inc
Normal file
@@ -0,0 +1,7 @@
|
||||
; CHIBI PC-09 Prototype #1 -- Reset Handler Header
|
||||
; Copyright (c) 2025 Amber Zeller, Gale Faraday
|
||||
; Licensed under MIT
|
||||
|
||||
; vim: ft=asm
|
||||
|
||||
RESET IMPORT
|
||||
45
src/reset.s
Normal file
45
src/reset.s
Normal file
@@ -0,0 +1,45 @@
|
||||
; CHIBI PC-09 Prototype #1 Boot ROM -- Reset Handler
|
||||
; Copyright (c) 2024-2025 Amber Zeller, Gale Faraday
|
||||
; Licensed under MIT
|
||||
|
||||
INCLUDE "hardware.inc"
|
||||
INCLUDE "serial.inc"
|
||||
INCLUDE "memtest.inc"
|
||||
INCLUDE "version.inc"
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Hardware Initialization Routines
|
||||
;;
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
|
||||
SECTION RESET
|
||||
|
||||
EXPORT RESET
|
||||
|
||||
RESET
|
||||
orcc #$50 ; Mask IRQ and FIRQ
|
||||
jsr INITUART ; Initialize serial console
|
||||
|
||||
CLRSTACK
|
||||
; Initialize the system stack
|
||||
lda #$00 ; Initialize A & X to zero out the stack
|
||||
ldx #$0000
|
||||
NEXT@
|
||||
sta STACK_BOTTOM,x ; Write a zero and progress to the next byte
|
||||
leax 1,x
|
||||
cmpx #STACK_DEPTH ; See if we're at the top of the stack yet
|
||||
blo NEXT@ ; Loop if we aren't at the end yet
|
||||
lds #STACK_TOP ; Set S to top of newly cleared stack
|
||||
|
||||
BOOTSCR
|
||||
ldx #VERMSG
|
||||
jsr POUTZSTR
|
||||
|
||||
; Progress to POST
|
||||
POST
|
||||
jsr RAMTEST
|
||||
|
||||
HALT
|
||||
sync ; Halt and wait for interrupts
|
||||
bra HALT
|
||||
9
src/serial.inc
Normal file
9
src/serial.inc
Normal file
@@ -0,0 +1,9 @@
|
||||
; CHIBI PC-09 Prototype #1 -- Serial Driver Header
|
||||
; Copyright (c) 2025 Amber Zeller, Gale Faraday
|
||||
; Licensed under MIT
|
||||
|
||||
; vim: ft=asm
|
||||
|
||||
INITUART IMPORT
|
||||
POUTCHAR IMPORT
|
||||
POUTZSTR IMPORT
|
||||
83
src/serial.s
Normal file
83
src/serial.s
Normal file
@@ -0,0 +1,83 @@
|
||||
; CHIBI PC-09 Prototype #1 Boot ROM -- Serial Driver
|
||||
; Copyright (c) 2024-2025 Amber Zeller, Gale Faraday
|
||||
; Licensed under MIT
|
||||
|
||||
INCLUDE "hardware.inc"
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Serial UART Driver
|
||||
;;
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
|
||||
SECTION SERIAL
|
||||
|
||||
EXPORT INITUART
|
||||
EXPORT POUTCHAR
|
||||
EXPORT POUTZSTR
|
||||
|
||||
; Initializes the UART with LCR settings and a BAUD rate from DIVISORS.
|
||||
; ACCA: Index of the divsor to use in DIVISORS
|
||||
; ACCB: Settings for LCR
|
||||
INITUART
|
||||
ldx #DIVISORS ; Get DIVISORS base addr
|
||||
asla ; Shift left to *2 the index in order to iter over words.
|
||||
pshs b ; Save B
|
||||
ldd a,x ; Get divisor into D
|
||||
sta UART_DLM ; Write divisor MSB
|
||||
stb UART_DLL ; Write divisor LSB
|
||||
lda UARTF_FCR_FE|UARTF_FCR_RFR|UARTF_FCR_XFR ; FIFO disable and clear
|
||||
sta UART_FCR
|
||||
lda #0
|
||||
sta UART_IER ; Polled mode
|
||||
sta UART_MCR ; Reset DTR, RTS
|
||||
rts
|
||||
|
||||
; Prints a character in polled non-FIFO mode (INITUART state).
|
||||
; ACCA: char to write
|
||||
POUTCHAR
|
||||
pshs a ; Preserve char
|
||||
NEXTC@
|
||||
lda UART_LSR ; Wait until LSR.THRE == 1 then write char
|
||||
bita UARTF_LSR_THRE
|
||||
beq NEXTC@
|
||||
puls a ; Restore char
|
||||
sta UART_THR ; Write char
|
||||
rts
|
||||
|
||||
; Prints a null terminated string in polled non-FIFO mode (INITUART state).
|
||||
; X: start of zstring
|
||||
POUTZSTR
|
||||
pshs a,b ; Preserve A and B
|
||||
NEXTC@
|
||||
ldb 0,x ; Get next char from X
|
||||
cmpb #$00 ; Make sure that we aren't at a terminator
|
||||
leax 1,x ; Increment X for next char. we inc here to save bytes if the
|
||||
; next string is adjacent.
|
||||
beq END@
|
||||
NOTREADY@
|
||||
lda UART_LSR ; Wait until LSR.THRE == 1 then write char
|
||||
bita UARTF_LSR_THRE
|
||||
beq NOTREADY@
|
||||
stb UART_THR ; Write char
|
||||
bra NEXTC@ ; Iter to next char
|
||||
END@
|
||||
puls b,a ; Restore A and B
|
||||
rts
|
||||
|
||||
DIVISORS
|
||||
fdb $0900 ; 50 baud
|
||||
fdb $0600 ; 75 baud
|
||||
fdb $0417 ; 110 baud
|
||||
fdb $0359 ; 134.5 baud
|
||||
fdb $0300 ; 150 baud
|
||||
fdb $0180 ; 300 baud
|
||||
fdb $00C0 ; 600 baud
|
||||
fdb $0060 ; 1200 baud
|
||||
fdb $0040 ; 1800 baud
|
||||
fdb $0030 ; 2400 baud
|
||||
fdb $0020 ; 3600 baud
|
||||
fdb $0018 ; 4800 baud
|
||||
fdb $0010 ; 7200 baud
|
||||
fdb $000C ; 9600 baud
|
||||
fdb $0006 ; 19200 baud
|
||||
23
src/vecs.s
Normal file
23
src/vecs.s
Normal file
@@ -0,0 +1,23 @@
|
||||
; CHIBI PC-09 Prototype #1 Boot ROM -- Interrupt and Reset Vectors
|
||||
; Copyright (c) 2024-2025 Amber Zeller, Gale Faraday
|
||||
; Licensed under MIT
|
||||
|
||||
INCLUDE "reset.inc"
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Interrupt and Reset Vectors
|
||||
;;
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
|
||||
SECTION VECTORS
|
||||
|
||||
VECTORS
|
||||
fdb $0000 ; Reserved
|
||||
fdb $0000 ; SWI3
|
||||
fdb $0000 ; SWI2
|
||||
fdb $0000 ; FIRQ
|
||||
fdb $0000 ; IRQ
|
||||
fdb $0000 ; SWI
|
||||
fdb $0000 ; NMI
|
||||
fdb RESET ; Reset
|
||||
7
src/version.inc
Normal file
7
src/version.inc
Normal file
@@ -0,0 +1,7 @@
|
||||
; CHIBI PC-09 Prototype #1 Boot ROM -- Version Information Header
|
||||
; Copyright (c) 2024-2025 Amber Zeller, Gale Faraday
|
||||
; Licensed under MIT
|
||||
|
||||
; vim: ft=asm
|
||||
|
||||
VERMSG IMPORT
|
||||
Reference in New Issue
Block a user