Populate repository from old progress; massive cleanup and fixes

2025-09-09 17:56:47 -05:00
parent 2695e5bb29
commit a0b654f160
15 changed files with 503 additions and 2 deletions
--- a/src/hardware.inc
+++ b/src/hardware.inc
@@ -0,0 +1,107 @@
+; CHIBI PC-09 Hardware Definitions
+; Copyright (c) 2024-2025 Amber Zeller, Gale Faraday
+; Licensed under MIT
+
+; vim: ft=asm
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Hardware Base Addresses
+;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+SRAM_BASE EQU $0000 ; SRAM Base Address
+UART_BASE EQU $7F00 ; UART Base Address
+ROM_BASE  EQU $8000 ; ROM Base Address and Entry Point
+VECS_BASE EQU $FFF0 ; Vectors Base Address
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Stack Base Address and Size Information
+;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+STACK_BOTTOM EQU $0100 ; Bottom address of system stack
+STACK_DEPTH  EQU $FF   ; System stack's depth
+STACK_TOP    EQU STACK_BOTTOM+STACK_DEPTH ; Top address of system stack
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; UART Registers and Flags
+;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; When UARTF_LCR_DLAB = 0:
+UART_BUFR EQU UART_BASE   ; TX/RX Buffer (Read for RX, Write for TX)
+UART_RBR  EQU UART_BASE   ; RX Buffer Register
+UART_THR  EQU UART_BASE   ; TX Holding Register
+UART_IER  EQU UART_BASE+1 ; Interrupt Enable Register
+
+; When UARTF_LCR_DLAB = 1:
+UART_DLL EQU UART_BASE   ; Divisor Latch (LSB)
+UART_DLM EQU UART_BASE+1 ; Divisor Latch (MSB)
+
+; Independent of DLAB:
+UART_IIR EQU UART_BASE+2 ; Interrupt Ident Register (Upon Read)
+UART_FCR EQU UART_BASE+2 ; FIFO Control Register (Upon Write)
+UART_LCR EQU UART_BASE+3 ; Line Control Register
+UART_MCR EQU UART_BASE+4 ; MODEM Control Register
+UART_LSR EQU UART_BASE+5 ; Line Status Register
+UART_MSR EQU UART_BASE+6 ; MODEM Status Register
+UART_SCR EQU UART_BASE+7 ; Scratch Register (Not for control just spare RAM)
+
+; UART Flags for Interrupt Enable Register:
+UARTF_IER_ERBFI EQU %00000001 ; Enable Received Data Available Interrupt
+UARTF_IER_ETBEI EQU %00000010 ; Enable Transmitter Holding Register Empty Interrupt
+UARTF_IER_ELSI  EQU %00000100 ; Enable Receiver Line Status Interrupt
+UARTF_IER_EDSSI EQU %00001000 ; Enable MODEM Status Interrupt
+
+; UART Flags for FIFO Control Register:
+UARTF_FCR_FE   EQU %00000001 ; FIFO Enabled
+UARTF_FCR_RFR  EQU %00000010 ; RCVR FIFO Reset
+UARTF_FCR_XFR  EQU %00000100 ; XMIT FIFO Reset
+UARTF_FCR_DMS  EQU %00001000 ; DMA Mode Select
+UARTF_FCR_RTL  EQU %01000000 ; RCVR Trigger (LSB)
+UARTF_FCR_RTM  EQU %10000000 ; RCVR Trigger (MSB)
+
+; UART Flags for Interrupt Ident Register:
+UARTF_IIR_INP  EQU %00000001 ; Reset if Interrupt Pending; 'INP' = Interrupt Not Pending
+UARTF_IIR_IIDM EQU %00001110 ; Interrupt ID Mask
+UARTF_IIR_FEM  EQU %11000000 ; FIFOs Enabled Mask
+
+; UART Flags for Line Control Register:
+UARTF_LCR_WLS  EQU %00000011 ; Word Length Select Bits
+UARTF_LCR_STB  EQU %00000100 ; Stop Bits
+UARTF_LCR_PEN  EQU %00001000 ; Parity Enable
+UARTF_LCR_EPS  EQU %00010000 ; Even Parity Select
+UARTF_LCR_SPR  EQU %00100000 ; Stick Parity
+UARTF_LCR_BRK  EQU %01000000 ; Set Break
+UARTF_LCR_DLAB EQU %10000000 ; Divisor Latch Access Bit
+
+; UART Flags for MODEM Control Register:
+UARTF_MCR_DTR  EQU %00000001 ; Data Terminal Ready
+UARTF_MCR_RTS  EQU %00000010 ; Enabling Request to Send
+UARTF_MCR_OUT1 EQU %00000100 ; Out 1
+UARTF_MCR_OUT2 EQU %00001000 ; Out 2
+UARTF_MCR_LOOP EQU %00010000 ; Loop
+
+; UART Flags for Line Status Register:
+UARTF_LSR_DR   EQU %00000001 ; Data Ready
+UARTF_LSR_OE   EQU %00000010 ; Overrun Error
+UARTF_LSR_PE   EQU %00000100 ; Parity Error
+UARTF_LSR_FE   EQU %00001000 ; Framing Error
+UARTF_LSR_BI   EQU %00010000 ; Break Interrupt
+UARTF_LSR_THRE EQU %00100000 ; Transmitter Holding Register
+UARTF_LSR_TEMT EQU %01000000 ; Transmitter Empty
+UARTF_LSR_FIFO EQU %10000000 ; Error in RCVR FIFO
+
+; UART Flags for MODEM Status Register:
+UARTF_MSR_DCTS EQU %00000001 ; Delta Clear to Send
+UARTF_MSR_DDSR EQU %00000010 ; Delta Data Set Ready
+UARTF_MSR_TERI EQU %00000100 ; Trailing Edge Ring Indicator
+UARTF_MSR_DDCD EQU %00001000 ; Delta Data Carrier Detect
+UARTF_MSR_CTS  EQU %00010000 ; Clear To Send
+UARTF_MSR_DSR  EQU %00100000 ; Data Set Ready
+UARTF_MSR_RI   EQU %01000000 ; Ring Indicator
+UARTF_MSR_DCD  EQU %10000000 ; Data Carrier Detect
+
--- a/src/memtest.inc
+++ b/src/memtest.inc
@@ -0,0 +1,7 @@
+; CHIBI PC-09 Prototype #1 -- Memory Testing Routines Header
+; Copyright (c) 2025 Amber Zeller, Gale Faraday
+; Licensed under MIT
+
+; vim: ft=asm
+
+RAMTEST IMPORT
--- a/src/memtest.s
+++ b/src/memtest.s
@@ -0,0 +1,44 @@
+; CHIBI PC-09 Prototype #1 Boot ROM -- Memory Testing Routines
+; Copyright (c) 2024-2025 Amber Zeller, Gale Faraday
+; Licensed under MIT
+
+  INCLUDE "hardware.inc"
+  INCLUDE "serial.inc"
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Memory Testing Routines
+;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+  SECTION MEMTEST
+
+  EXPORT RAMTEST
+
+; RAM testing routine. Ported to 6809 from 6800, based on source for ROBIT-2 for
+; MIKBUG.
+RAMTEST
+  ldx #SRAM_BASE
+AGAIN@                 ; Store 1 in memory
+  lda #1               ; Set [X] to 1
+  sta 0,x
+  cmpa 0,x             ; If failed print out an error indicator
+  bne ERR@
+NEXT@                  ; Loop point for next address
+  asla                 ; Shift A and [X] left
+  asl 0,x
+  cmpa 0,x             ; Compare A and [X]
+  bne ERR@
+  cmpa #$80            ; Only test up to $80
+  bne NEXT@            ; Loop if not $80
+  cmpx #$60FF          ; Compare X to end of RAM
+  beq PASS@            ; Finish if we're at the end
+  leax 1,x             ; Increment X
+  bra AGAIN@
+ERR@                   ; Write out error indicator
+  ldb #'X
+  jsr POUTCHAR
+PASS@                  ; Pass test
+  ldb #'P
+  jsr POUTCHAR
+  rts
--- a/src/reset.inc
+++ b/src/reset.inc
@@ -0,0 +1,7 @@
+; CHIBI PC-09 Prototype #1 -- Reset Handler Header
+; Copyright (c) 2025 Amber Zeller, Gale Faraday
+; Licensed under MIT
+
+; vim: ft=asm
+
+RESET IMPORT
--- a/src/reset.s
+++ b/src/reset.s
@@ -0,0 +1,45 @@
+; CHIBI PC-09 Prototype #1 Boot ROM -- Reset Handler
+; Copyright (c) 2024-2025 Amber Zeller, Gale Faraday
+; Licensed under MIT
+
+  INCLUDE "hardware.inc"
+  INCLUDE "serial.inc"
+  INCLUDE "memtest.inc"
+  INCLUDE "version.inc"
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Hardware Initialization Routines
+;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+  SECTION RESET
+
+  EXPORT RESET
+
+RESET
+  orcc #$50    ; Mask IRQ and FIRQ
+  jsr INITUART ; Initialize serial console
+
+CLRSTACK
+  ; Initialize the system stack
+  lda #$00           ; Initialize A & X to zero out the stack
+  ldx #$0000
+NEXT@
+  sta STACK_BOTTOM,x ; Write a zero and progress to the next byte
+  leax 1,x
+  cmpx #STACK_DEPTH  ; See if we're at the top of the stack yet
+  blo NEXT@          ; Loop if we aren't at the end yet
+  lds #STACK_TOP     ; Set S to top of newly cleared stack
+
+BOOTSCR
+  ldx #VERMSG
+  jsr POUTZSTR
+
+; Progress to POST
+POST
+  jsr RAMTEST
+
+HALT
+  sync                 ; Halt and wait for interrupts
+  bra HALT
--- a/src/serial.inc
+++ b/src/serial.inc
@@ -0,0 +1,9 @@
+; CHIBI PC-09 Prototype #1 -- Serial Driver Header
+; Copyright (c) 2025 Amber Zeller, Gale Faraday
+; Licensed under MIT
+
+; vim: ft=asm
+
+INITUART IMPORT
+POUTCHAR IMPORT
+POUTZSTR IMPORT
--- a/src/serial.s
+++ b/src/serial.s
@@ -0,0 +1,83 @@
+; CHIBI PC-09 Prototype #1 Boot ROM -- Serial Driver
+; Copyright (c) 2024-2025 Amber Zeller, Gale Faraday
+; Licensed under MIT
+
+  INCLUDE "hardware.inc"
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Serial UART Driver
+;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+  SECTION SERIAL
+
+  EXPORT INITUART
+  EXPORT POUTCHAR
+  EXPORT POUTZSTR
+
+; Initializes the UART with LCR settings and a BAUD rate from DIVISORS.
+; ACCA: Index of the divsor to use in DIVISORS
+; ACCB: Settings for LCR
+INITUART
+  ldx #DIVISORS ; Get DIVISORS base addr
+  asla          ; Shift left to *2 the index in order to iter over words.
+  pshs b        ; Save B
+  ldd a,x       ; Get divisor into D
+  sta UART_DLM  ; Write divisor MSB
+  stb UART_DLL  ; Write divisor LSB
+  lda UARTF_FCR_FE|UARTF_FCR_RFR|UARTF_FCR_XFR ; FIFO disable and clear
+  sta UART_FCR
+  lda #0
+  sta UART_IER  ; Polled mode
+  sta UART_MCR  ; Reset DTR, RTS
+  rts
+
+; Prints a character in polled non-FIFO mode (INITUART state).
+; ACCA: char to write
+POUTCHAR
+  pshs a       ; Preserve char
+NEXTC@
+  lda UART_LSR ; Wait until LSR.THRE == 1 then write char
+  bita UARTF_LSR_THRE
+  beq NEXTC@
+  puls a       ; Restore char
+  sta UART_THR ; Write char
+  rts
+
+; Prints a null terminated string in polled non-FIFO mode (INITUART state).
+; X: start of zstring
+POUTZSTR
+  pshs a,b     ; Preserve A and B
+NEXTC@
+  ldb 0,x      ; Get next char from X
+  cmpb #$00    ; Make sure that we aren't at a terminator
+  leax 1,x     ; Increment X for next char. we inc here to save bytes if the
+               ; next string is adjacent.
+  beq END@
+NOTREADY@
+  lda UART_LSR ; Wait until LSR.THRE == 1 then write char
+  bita UARTF_LSR_THRE
+  beq NOTREADY@
+  stb UART_THR ; Write char
+  bra NEXTC@   ; Iter to next char
+END@
+  puls b,a     ; Restore A and B
+  rts
+
+DIVISORS
+  fdb $0900 ; 50 baud
+  fdb $0600 ; 75 baud
+  fdb $0417 ; 110 baud
+  fdb $0359 ; 134.5 baud
+  fdb $0300 ; 150 baud
+  fdb $0180 ; 300 baud
+  fdb $00C0 ; 600 baud
+  fdb $0060 ; 1200 baud
+  fdb $0040 ; 1800 baud
+  fdb $0030 ; 2400 baud
+  fdb $0020 ; 3600 baud
+  fdb $0018 ; 4800 baud
+  fdb $0010 ; 7200 baud
+  fdb $000C ; 9600 baud
+  fdb $0006 ; 19200 baud
--- a/src/vecs.s
+++ b/src/vecs.s
@@ -0,0 +1,23 @@
+; CHIBI PC-09 Prototype #1 Boot ROM -- Interrupt and Reset Vectors
+; Copyright (c) 2024-2025 Amber Zeller, Gale Faraday
+; Licensed under MIT
+
+  INCLUDE "reset.inc"
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Interrupt and Reset Vectors
+;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+  SECTION VECTORS
+
+VECTORS
+  fdb $0000 ; Reserved
+  fdb $0000 ; SWI3
+  fdb $0000 ; SWI2
+  fdb $0000 ; FIRQ
+  fdb $0000 ; IRQ
+  fdb $0000 ; SWI
+  fdb $0000 ; NMI
+  fdb RESET ; Reset
--- a/src/version.inc
+++ b/src/version.inc
@@ -0,0 +1,7 @@
+; CHIBI PC-09 Prototype #1 Boot ROM -- Version Information Header
+; Copyright (c) 2024-2025 Amber Zeller, Gale Faraday
+; Licensed under MIT
+
+; vim: ft=asm
+
+VERMSG IMPORT