feat(boot): new baud setup routine

code/boot/README.md

@@ -1,31 +1,35 @@
 # Boot Firmware for CHIBI PC-09
 
-TODO: Description of what the firmware does for the PC-09.
+This is the firmware for the CHIBI PC-09. In the future it will provide the
+CHIBI with initialization code, a UART driver, some self test features.
 
 ## Building the Firmware
 
-You will need GNU `make`, and [`asm6809`](https://www.6809.org.uk/asm6809) to
-build the firmware. Obtaining a working copy of `asm6809` could be difficult if
-you aren't on Debian, Ubuntu, or Windows as instructions for building it are not
-given on the `asm6809` website. Functional instructions for building from Git or
-tarball are given here:
+Building the firmware from source requires [LWTOOLS](http://www.lwtools.ca/) for
+building S-Records of the ROM, and `mot2bin` from
+[F9DASM](https://github.com/Arakula/f9dasm) for building binary images. A GNU
+Make makefile is provided for building on Linux.
+
+### Using the Makefile
+
+To generate an S-Record run:
 
 ```sh
-git clone https://www.6809.org.uk/git/asm6809.git
-cd asm6809
-./configure
-make
-sudo make install
+make boot.s19
 ```
 
-From there all you should have to do to generate a `boot.bin` is:
+To generate a binary run:
 
 ```sh
-git clone https://github.com/amberisvibin/chibi-pc09.git
-cd chibi-pc09/code/boot
 make
 ```
 
+The makefile also can clean up after itself:
+
+```sh
+make clean
+```
+
 ## Firmware Licensing
 
 This firmware like the rest of the CHIBI PC-09 is licensed under the MIT

code/boot/makefile

@@ -8,13 +8,14 @@
 # Project Defaults & Folders
 # ------------------------------------------------------------------------------
 
-TARGET  := boot
-TARGROM := $(TARGET).bin
-SRCDIR  := src/
+TARGET   := boot
+TARGREC  := $(TARGET).s19
+TARGROM  := $(TARGET).bin
+SRCDIR   := src/
 BUILDDIR := build/
-SRCS    := $(wildcard $(SRCDIR)*.s)
-OBJS    := $(patsubst $(SRCDIR)%.s,$(BUILDDIR)%.o,$(SRCS))
-INCS    := $(wildcard $(SRCDIR)*.inc)
+SRCS     := $(wildcard $(SRCDIR)*.s)
+OBJS     := $(patsubst $(SRCDIR)%.s,$(BUILDDIR)%.o,$(SRCS))
+INCS     := $(wildcard $(SRCDIR)*.inc)
 
 # ------------------------------------------------------------------------------
 # Toolchain Definitions
@@ -22,7 +23,7 @@ INCS    := $(wildcard $(SRCDIR)*.inc)
 
 AS  := lwasm
 LD  := lwlink
-FIX := mot2bin
+FIX := objcopy
 
 ASFLAGS := -f obj
 LDFLAGS := -f srec -m map.txt -s linkscript
@@ -34,11 +35,11 @@ LDFLAGS := -f srec -m map.txt -s linkscript
 all: $(TARGROM)
 
 # Fix srec into flashable bin file
-$(TARGROM): $(TARGET).s19
-	$(FIX) -out $@ $<
+$(TARGROM): $(TARGREC)
+	$(FIX) -I srec -O binary $< $@
 
 # Link objects
-$(TARGET).s19: $(OBJS)
+$(TARGREC): $(OBJS)
 	$(LD) $(LDFLAGS) -o $@ $^
 
 # Assemble objects
@@ -46,7 +47,6 @@ $(OBJS): $(BUILDDIR)%.o : $(SRCDIR)%.s
 	-@mkdir -p $(BUILDDIR)
 	$(AS) $(ASFLAGS) -o $@ $<
 
-.IGNORE: clean
 clean:
 	@echo 'Cleaning up intermediary files...'
-	@rm -rv $(TARGROM) $(TARGET).s19 map.txt $(BUILDDIR)
+	@rm -rv $(TARGROM) $(TARGREC) map.txt $(BUILDDIR)

code/boot/src/hardware.inc

@@ -15,6 +15,16 @@ UART_BASE EQU $7F00 ; UART Base Address
 ROM_BASE  EQU $8000 ; ROM Base Address and Entry Point
 VECS_BASE EQU $FFF0 ; Vectors Base Address
 
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Stack Base Address and Size Information
+;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+STACK_BOTTOM EQU $0100 ; Bottom address of system stack
+STACK_DEPTH  EQU $FF   ; System stack's depth
+STACK_TOP    EQU STACK_BOTTOM+STACK_DEPTH ; Top address of system stack
+
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;;
 ;; UART Registers and Flags

code/boot/src/reset.s

@@ -16,8 +16,21 @@
   EXPORT RESET
 
 RESET
+
+CLRSTACK
+  ; Initialize the system stack
+  lda #$00           ; Initialize A & X to zero out the stack
+  ldx #$0000
+NEXT@
+  sta STACK_BOTTOM,x ; Write a zero and progress to the next byte
+  leax 1,x
+  cmpx #STACK_DEPTH  ; See if we're at the top of the stack yet
+  blo NEXT@          ; Loop if we aren't at the end yet
+  lds STACK_TOP      ; Set S to top of newly cleared stack
+
+SERINIT
   ; 8n1 Serial Enable DLAB
-  lda #UARTF_LCR_WLS | UARTF_LCR_DLAB
+  lda #UARTF_LCR_WLS|UARTF_LCR_DLAB
   sta UART_LCR
   ; REVIEW: Potential endianness hiccough here
   ldd #$0C00           ; Set divisor to 12 (9600 baud)
@@ -28,8 +41,9 @@ RESET
   lda #(UARTF_MCR_RTS) ; Enable Request-to-Send
   sta UART_MCR
   lda #'H               ; send 'H'
-  sta UART_BUFR
-WAIT@
+  sta UART_THR
+
+WAIT
   sync                 ; Wait for interrupts
   nop
-  bra WAIT@
+  bra WAIT

code/boot/src/serial.s

@@ -12,9 +12,25 @@
 
   SECTION SERIAL
 
+  EXPORT SETBAUD
   EXPORT OUTCHAR
   EXPORT OUTSTR
 
+; Initializes the UART.
+; @param d: new divisor
+SETBAUD
+  pshs a              ; Preserve A
+  lda UART_LCR        ; Set only the DLAB bit
+  ora #UARTF_LCR_DLAB
+  sta UART_LCR
+  puls a
+  sta UART_DLM        ; Store new divisor
+  stb UART_DLL
+  lda UART_LCR        ; Reset DLAB
+  anda #$FE
+  sta UART_LCR
+  rts
+
 ; Writes a char to the UART in non FIFO mode, preserves A.
 ; @param b: char to write
 OUTCHAR
@@ -23,7 +39,7 @@ NOTREADY@
   lda UART_LSR         ; if LSR.THRE == 1 then write
   anda UARTF_LSR_THRE
   bne NOTREADY@        ; Loop if UART not ready yet
-  stb UART_BUFR        ; Write char
+  stb UART_THR         ; Write char
   puls a               ; Restore A
   rts
 
@@ -39,7 +55,7 @@ NOTREADY@              ; Loop point for UART waiting
   lda UART_LSR         ; Wait for UART to be ready
   anda UARTF_LSR_THRE
   bne NOTREADY@
-  stb UART_BUFR        ; Actually do our write
+  stb UART_THR         ; Actually do our write
   bra OUTSTR           ; Reset for the next char
 END@                   ; Jump point for end of routine
   rts