Merge pull request #12 from amberisvibin/hardware.inc
Setup hardware.inc
This commit is contained in:
Amber
@@ -8,7 +8,7 @@ charset = utf-8
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trim_trailing_whitespace = true
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insert_final_newline = true
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[*.s]
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[*.{s,inc}]
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indent_style = space
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indent_size = 2
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@@ -10,21 +10,21 @@
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;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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ORG $8000
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ORG ROM_BASE
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RESET
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lda %11000001 ; 8n1 serial, enable DLAB
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lda #%11000001 ; 8n1 serial, enable DLAB
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sta UART_LCR
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lda $00 ; Set divisor to 12 (9600 baud)
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lda #$00 ; Set divisor to 12 (9600 baud)
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sta UART_DLL
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lda $0C
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lda #$0C
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sta UART_DLM
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lda %11000000 ; 8n1 serial, disable DLAB
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lda #%11000000 ; 8n1 serial, disable DLAB
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sta UART_LCR
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lda %01000000 ; Enable RTS
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lda #%01000000 ; Enable RTS
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sta UART_MCR
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lda 'H ; send 'H'
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@@ -41,7 +41,7 @@ WAIT
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;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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ORG $FFF0
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ORG VECS_BASE
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VECTORS
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fdb $0000 ; Reserved
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@@ -8,7 +8,10 @@
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;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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SRAM_BASE EQU $0000 ; SRAM Base Address
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UART_BASE EQU $7F00 ; UART Base Address
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ROM_BASE EQU $8000 ; ROM Base Address and Entry Point
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VECS_BASE EQU $FFF0 ; Vectors Base Address
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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@@ -16,15 +19,18 @@ UART_BASE EQU $7F00 ; UART Base Address
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;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; When UARTF_DLAB = 0:
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; When UARTF_LCR_DLAB = 0:
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UART_BUFR EQU UART_BASE ; TX/RX Buffer (Read for RX, Write for TX)
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UART_RBR EQU UART_BASE ; RX Buffer Register
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UART_THR EQU UART_BASE ; TX Holding Register
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UART_IER EQU UART_BASE + 1 ; Interrupt Enable Register
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UART_IIR EQU UART_BASE + 1 ; Interrupt Ident Register (Upon Read)
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; When UARTF_DLAB = 1:
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; When UARTF_LCR_DLAB = 1:
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UART_DLL EQU UART_BASE ; Divisor Latch (LSB)
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UART_DLM EQU UART_BASE + 1 ; Divisor Latch (MSB)
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; Independent of DLAB:
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UART_IIR EQU UART_BASE + 2 ; Interrupt Ident Register (Upon Read)
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UART_FCR EQU UART_BASE + 2 ; FIFO Control Register (Upon Write)
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UART_LCR EQU UART_BASE + 3 ; Line Control Register
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UART_MCR EQU UART_BASE + 4 ; MODEM Control Register
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@@ -32,5 +38,59 @@ UART_LSR EQU UART_BASE + 5 ; Line Status Register
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UART_MSR EQU UART_BASE + 6 ; MODEM Status Register
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UART_SCR EQU UART_BASE + 7 ; Scratch Register (Not for control just spare RAM)
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; UART Flags
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UARTF_DLAB EQU %00000001
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; UART Flags for Interrupt Enable Register:
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UARTF_IER_ERBFI EQU %10000000 ; Enable Received Data Available Interrupt
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UARTF_IER_ETBEI EQU %01000000 ; Enable Transmitter Holding Register Empty Interrupt
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UARTF_IER_ELSI EQU %00100000 ; Enable Receiver Line Status Interrupt
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UARTF_IER_EDSSI EQU %00010000 ; Enable MODEM Status Interrupt
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; UART Flags for FIFO Control Register:
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UARTF_FCR_FE EQU %10000000 ; FIFO Enabled
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UARTF_FCR_RFR EQU %01000000 ; RCVR FIFO Reset
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UARTF_FCR_XFR EQU %00100000 ; XMIT FIFO Reset
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UARTF_FCR_DMS EQU %00010000 ; DMA Mode Select
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UARTF_FCR_RTL EQU %00000010 ; RCVR Trigger (LSB)
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UARTF_FCR_RTM EQU %00000001 ; RCVR Trigger (MSB)
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; UART Flags for Interrupt Ident Register:
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UARTF_IIR_INP EQU %10000000 ; Reset if Interrupt Pending; 'INP' = Interrupt Not Pending
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UARTF_IIR_IIDM EQU %01110000 ; Interrupt ID Mask
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UARTF_IIR_FEM EQU %00000011 ; FIFOs Enabled Mask
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; UART Flags for Line Control Register:
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UARTF_LCR_WLS EQU %11000000 ; Word Length Select Bits
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UARTF_LCR_STB EQU %00100000 ; Stop Bits
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UARTF_LCR_PEN EQU %00010000 ; Parity Enable
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UARTF_LCR_EPS EQU %00001000 ; Even Parity Select
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UARTF_LCR_SPR EQU %00000100 ; Stick Parity
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UARTF_LCR_BRK EQU %00000010 ; Set Break
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UARTF_LCR_DLAB EQU %00000001 ; Divisor Latch Access Bit
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; UART Flags for MODEM Control Register:
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UARTF_MCR_DTR EQU %10000000 ; Data Terminal Ready
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UARTF_MCR_RTS EQU %01000000 ; Enabling Request to Send
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UARTF_MCR_OUT1 EQU %00100000 ; Out 1
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UARTF_MCR_OUT2 EQU %00010000 ; Out 2
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UARTF_MCR_LOOP EQU %00001000 ; Loop
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; UART Flags for Line Status Register:
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UARTF_LSR_DR EQU %10000000 ; Data Ready
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UARTF_LSR_OE EQU %01000000 ; Overrun Error
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UARTF_LSR_PE EQU %00100000 ; Parity Error
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UARTF_LSR_FE EQU %00010000 ; Framing Error
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UARTF_LSR_BI EQU %00001000 ; Break Interrupt
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UARTF_LSR_THRE EQU %00000100 ; Transmitter Holding Register
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UARTF_LSR_TEMT EQU %00000010 ; Transmitter Empty
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UARTF_LSR_FIFO EQU %00000001 ; Error in RCVR FIFO
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; UART Flags for MODEM Status Register:
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UARTF_MSR_DCTS EQU %10000000 ; Delta Clear to Send
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UARTF_MSR_DDSR EQU %01000000 ; Delta Data Set Ready
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UARTF_MSR_TERI EQU %00100000 ; Trailing Edge Ring Indicator
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UARTF_MSR_DDCD EQU %00010000 ; Delta Data Carrier Detect
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UARTF_MSR_CTS EQU %00001000 ; Clear To Send
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UARTF_MSR_DSR EQU %00000100 ; Data Set Ready
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UARTF_MSR_RI EQU %00000010 ; Ring Indicator
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UARTF_MSR_DCD EQU %00000001 ; Data Carrier Detect
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; vim: ft=asm
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