From 616e95bb0a0eb5d5d3a8c63a0fb207bc681f9a15 Mon Sep 17 00:00:00 2001 From: Gale Faraday Date: Thu, 28 Nov 2024 22:54:00 -0600 Subject: [PATCH 01/13] chore: added ROM_BASE and VECS_BASE to hardware.inc --- code/boot/src/boot.s | 4 ++-- code/boot/src/hardware.inc | 2 ++ 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/code/boot/src/boot.s b/code/boot/src/boot.s index 94f875c..3788d48 100644 --- a/code/boot/src/boot.s +++ b/code/boot/src/boot.s @@ -10,7 +10,7 @@ ;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - ORG $8000 + ORG ROM_BASE RESET lda %11000001 ; 8n1 serial, enable DLAB @@ -41,7 +41,7 @@ WAIT ;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - ORG $FFF0 + ORG VECS_BASE VECTORS fdb $0000 ; Reserved diff --git a/code/boot/src/hardware.inc b/code/boot/src/hardware.inc index 8aa186e..bf12ea0 100644 --- a/code/boot/src/hardware.inc +++ b/code/boot/src/hardware.inc @@ -9,6 +9,8 @@ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; UART_BASE EQU $7F00 ; UART Base Address +ROM_BASE EQU $8000 ; ROM Base Address and Entry Point +VECS_BASE EQU $FFF0 ; Vectors Base Address ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; From 10491c65e70dbdf4c039258e461235737c419c73 Mon Sep 17 00:00:00 2001 From: Gale Faraday Date: Thu, 28 Nov 2024 22:55:57 -0600 Subject: [PATCH 02/13] style: removed pointless newline --- code/boot/src/hardware.inc | 1 - 1 file changed, 1 deletion(-) diff --git a/code/boot/src/hardware.inc b/code/boot/src/hardware.inc index bf12ea0..d2c2ca9 100644 --- a/code/boot/src/hardware.inc +++ b/code/boot/src/hardware.inc @@ -26,7 +26,6 @@ UART_IIR EQU UART_BASE + 1 ; Interrupt Ident Register (Upon Read) ; When UARTF_DLAB = 1: UART_DLL EQU UART_BASE ; Divisor Latch (LSB) UART_DLM EQU UART_BASE + 1 ; Divisor Latch (MSB) - UART_FCR EQU UART_BASE + 2 ; FIFO Control Register (Upon Write) UART_LCR EQU UART_BASE + 3 ; Line Control Register UART_MCR EQU UART_BASE + 4 ; MODEM Control Register From 0b0fd1f83e9137c61f7f1d025e81f66e43eb7f62 Mon Sep 17 00:00:00 2001 From: Gale Faraday Date: Thu, 28 Nov 2024 23:16:45 -0600 Subject: [PATCH 03/13] chore: added SRAM_BASE to hardware.inc. --- code/boot/src/hardware.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/code/boot/src/hardware.inc b/code/boot/src/hardware.inc index d2c2ca9..d971432 100644 --- a/code/boot/src/hardware.inc +++ b/code/boot/src/hardware.inc @@ -8,6 +8,7 @@ ;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +SRAM_BASE EQU $0000 ; SRAM Base Address UART_BASE EQU $7F00 ; UART Base Address ROM_BASE EQU $8000 ; ROM Base Address and Entry Point VECS_BASE EQU $FFF0 ; Vectors Base Address From 088f5d838c7c56ba10070e8e7e5483dc073de111 Mon Sep 17 00:00:00 2001 From: Gale Faraday Date: Fri, 29 Nov 2024 09:30:00 -0600 Subject: [PATCH 04/13] fix: added vim ft=asm to inc file. --- code/boot/src/hardware.inc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/code/boot/src/hardware.inc b/code/boot/src/hardware.inc index d971432..27fab14 100644 --- a/code/boot/src/hardware.inc +++ b/code/boot/src/hardware.inc @@ -36,3 +36,5 @@ UART_SCR EQU UART_BASE + 7 ; Scratch Register (Not for control just spare RAM) ; UART Flags UARTF_DLAB EQU %00000001 + +; vim: ft=asm From e66019f9ac1958fee4afc71427efdbb655f21ca2 Mon Sep 17 00:00:00 2001 From: Gale Faraday Date: Fri, 29 Nov 2024 10:09:46 -0600 Subject: [PATCH 05/13] chore: added .inc to editorconfig rules. --- code/boot/.editorconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/code/boot/.editorconfig b/code/boot/.editorconfig index d657257..bbb4336 100644 --- a/code/boot/.editorconfig +++ b/code/boot/.editorconfig @@ -8,7 +8,7 @@ charset = utf-8 trim_trailing_whitespace = true insert_final_newline = true -[*.s] +[*.{s,inc}] indent_style = space indent_size = 2 From 83029f6617103c3551d6d1568608b813cd42fbb4 Mon Sep 17 00:00:00 2001 From: Gale Faraday Date: Fri, 29 Nov 2024 10:10:23 -0600 Subject: [PATCH 06/13] chore: added flag for 8n1 serial --- code/boot/src/hardware.inc | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/code/boot/src/hardware.inc b/code/boot/src/hardware.inc index 27fab14..e007f6e 100644 --- a/code/boot/src/hardware.inc +++ b/code/boot/src/hardware.inc @@ -10,7 +10,7 @@ SRAM_BASE EQU $0000 ; SRAM Base Address UART_BASE EQU $7F00 ; UART Base Address -ROM_BASE EQU $8000 ; ROM Base Address and Entry Point +ROM_BASE EQU $8000 ; ROM Base Address and Entry Point VECS_BASE EQU $FFF0 ; Vectors Base Address ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; @@ -34,7 +34,8 @@ UART_LSR EQU UART_BASE + 5 ; Line Status Register UART_MSR EQU UART_BASE + 6 ; MODEM Status Register UART_SCR EQU UART_BASE + 7 ; Scratch Register (Not for control just spare RAM) -; UART Flags -UARTF_DLAB EQU %00000001 +; UART Flags: +UARTF_DLAB EQU %00000001 ; Divisor Latch Access Bit +UARTF_8N1 EQU %11000000 ; 8n1 Serial Mode ; vim: ft=asm From d1cbc09e9990c2f9aef928e046360fe9100d1170 Mon Sep 17 00:00:00 2001 From: Gale Faraday Date: Fri, 29 Nov 2024 10:10:48 -0600 Subject: [PATCH 07/13] fix: fixed immediate values --- code/boot/src/boot.s | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/code/boot/src/boot.s b/code/boot/src/boot.s index 3788d48..6dfac52 100644 --- a/code/boot/src/boot.s +++ b/code/boot/src/boot.s @@ -13,25 +13,25 @@ ORG ROM_BASE RESET - lda %11000001 ; 8n1 serial, enable DLAB + lda #%11000001 ; 8n1 serial, enable DLAB sta UART_LCR - lda $00 ; Set divisor to 12 (9600 baud) + lda #$00 ; Set divisor to 12 (9600 baud) sta UART_DLL - lda $0C + lda #$0C sta UART_DLM - lda %11000000 ; 8n1 serial, disable DLAB + lda #%11000000 ; 8n1 serial, disable DLAB sta UART_LCR - lda %01000000 ; Enable RTS + lda #%01000000 ; Enable RTS sta UART_MCR lda 'H ; send 'H' sta UART_BUFR WAIT - sync ; Wait for interrupts + sync ; Wait for interrupts nop bra WAIT From 1294ac41d1e85ea2f7009419ec2fae05ef0cd69e Mon Sep 17 00:00:00 2001 From: Gale Faraday Date: Thu, 5 Dec 2024 12:23:31 -0600 Subject: [PATCH 08/13] feat(hardware.inc): added flags for LCR, MCR, and LSR. --- code/boot/src/hardware.inc | 40 ++++++++++++++++++++++++++++++++------ 1 file changed, 34 insertions(+), 6 deletions(-) diff --git a/code/boot/src/hardware.inc b/code/boot/src/hardware.inc index e007f6e..1ef1848 100644 --- a/code/boot/src/hardware.inc +++ b/code/boot/src/hardware.inc @@ -19,14 +19,18 @@ VECS_BASE EQU $FFF0 ; Vectors Base Address ;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; When UARTF_DLAB = 0: +; When UARTF_LCR_DLAB = 0: UART_BUFR EQU UART_BASE ; TX/RX Buffer (Read for RX, Write for TX) +UART_RBR EQU UART_BASE ; RX Buffer Register +UART_THR EQU UART_BASE ; TX Holding Register UART_IER EQU UART_BASE + 1 ; Interrupt Enable Register -UART_IIR EQU UART_BASE + 1 ; Interrupt Ident Register (Upon Read) -; When UARTF_DLAB = 1: +; When UARTF_LCR_DLAB = 1: UART_DLL EQU UART_BASE ; Divisor Latch (LSB) UART_DLM EQU UART_BASE + 1 ; Divisor Latch (MSB) + +; Independent of DLAB: +UART_IIR EQU UART_BASE + 2 ; Interrupt Ident Register (Upon Read) UART_FCR EQU UART_BASE + 2 ; FIFO Control Register (Upon Write) UART_LCR EQU UART_BASE + 3 ; Line Control Register UART_MCR EQU UART_BASE + 4 ; MODEM Control Register @@ -34,8 +38,32 @@ UART_LSR EQU UART_BASE + 5 ; Line Status Register UART_MSR EQU UART_BASE + 6 ; MODEM Status Register UART_SCR EQU UART_BASE + 7 ; Scratch Register (Not for control just spare RAM) -; UART Flags: -UARTF_DLAB EQU %00000001 ; Divisor Latch Access Bit -UARTF_8N1 EQU %11000000 ; 8n1 Serial Mode +; TODO: Flags for IER, IIR, FCR, and MSR + +; UART Flags for Line Control Register: +UARTF_LCR_8N1 EQU %11000000 ; 8n1 Serial Mode +UARTF_LCR_STB EQU %00100000 ; Stop Bits +UARTF_LCR_PEN EQU %00010000 ; Parity Enable +UARTF_LCR_EPS EQU %00001000 ; Even Parity Select +UARTF_LCR_SPR EQU %00000100 ; Stick Parity +UARTF_LCR_BRK EQU %00000010 ; Set Break +UARTF_LCR_DLAB EQU %00000001 ; Divisor Latch Access Bit + +; UART Flags for Modem Control Register: +UARTF_MCR_DTR EQU %10000000 ; Data Terminal Ready +UARTF_MCR_RTS EQU %01000000 ; Enabling Request to Send +UARTF_MCR_OUT1 EQU %00100000 ; Out 1 +UARTF_MCR_OUT2 EQU %00010000 ; Out 2 +UARTF_MCR_LOOP EQU %00001000 ; Loop + +; UART Flags for Line Status Register: +UARTF_LSR_DR EQU %10000000 ; Data Ready +UARTF_LSR_OE EQU %01000000 ; Overrun Error +UARTF_LSR_PE EQU %00100000 ; Parity Error +UARTF_LSR_FE EQU %00010000 ; Framing Error +UARTF_LSR_BI EQU %00001000 ; Break Interrupt +UARTF_LSR_THRE EQU %00000100 ; Transmitter Holding Register +UARTF_LSR_TEMT EQU %00000010 ; Transmitter Empty +UARTF_LSR_FIFO EQU %00000001 ; Error in RCVR FIFO ; vim: ft=asm From b3ebe917a96576d9aaebe5d8b6ed6cdfc8785f66 Mon Sep 17 00:00:00 2001 From: Gale Faraday Date: Thu, 5 Dec 2024 12:28:58 -0600 Subject: [PATCH 09/13] feat(hardware.inc): added flags for MSR. --- code/boot/src/hardware.inc | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/code/boot/src/hardware.inc b/code/boot/src/hardware.inc index 1ef1848..0634390 100644 --- a/code/boot/src/hardware.inc +++ b/code/boot/src/hardware.inc @@ -38,7 +38,7 @@ UART_LSR EQU UART_BASE + 5 ; Line Status Register UART_MSR EQU UART_BASE + 6 ; MODEM Status Register UART_SCR EQU UART_BASE + 7 ; Scratch Register (Not for control just spare RAM) -; TODO: Flags for IER, IIR, FCR, and MSR +; TODO: Flags for IER, IIR, FCR ; UART Flags for Line Control Register: UARTF_LCR_8N1 EQU %11000000 ; 8n1 Serial Mode @@ -66,4 +66,14 @@ UARTF_LSR_THRE EQU %00000100 ; Transmitter Holding Register UARTF_LSR_TEMT EQU %00000010 ; Transmitter Empty UARTF_LSR_FIFO EQU %00000001 ; Error in RCVR FIFO +; UART Flags for Modem Status Register: +UARTF_MSR_DCTS EQU %10000000 ; Delta Clear to Send +UARTF_MSR_DDSR EQU %01000000 ; Delta Data Set Ready +UARTF_MSR_TERI EQU %00100000 ; Trailing Edge Ring Indicator +UARTF_MSR_DDCD EQU %00010000 ; Delta Data Carrier Detect +UARTF_MSR_CTS EQU %00001000 ; Clear To Send +UARTF_MSR_DSR EQU %00000100 ; Data Set Ready +UARTF_MSR_RI EQU %00000010 ; Ring Indicator +UARTF_MSR_DCD EQU %00000001 ; Data Carrier Detect + ; vim: ft=asm From 7d03e97d94630c37362bb8a80a029f8a26897efe Mon Sep 17 00:00:00 2001 From: Gale Faraday Date: Thu, 5 Dec 2024 14:45:45 -0600 Subject: [PATCH 10/13] feat(hardware.inc): added flags for IER and changed 'Modem'->'MODEM' --- code/boot/src/hardware.inc | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/code/boot/src/hardware.inc b/code/boot/src/hardware.inc index 0634390..7eb25b7 100644 --- a/code/boot/src/hardware.inc +++ b/code/boot/src/hardware.inc @@ -38,7 +38,13 @@ UART_LSR EQU UART_BASE + 5 ; Line Status Register UART_MSR EQU UART_BASE + 6 ; MODEM Status Register UART_SCR EQU UART_BASE + 7 ; Scratch Register (Not for control just spare RAM) -; TODO: Flags for IER, IIR, FCR +; TODO: Flags for IIR, FCR + +; UART Flags for Interrupt Enable Register: +UARTF_IER_ERBFI EQU %10000000 ; Enable Received Data Available Interrupt +UARTF_IER_ETBEI EQU %01000000 ; Enable Transmitter Holding Register Empty Interrupt +UARTF_IER_ELSI EQU %00100000 ; Enable Receiver Line Status Interrupt +UARTF_IER_EDSSI EQU %00010000 ; Enable MODEM Status Interrupt ; UART Flags for Line Control Register: UARTF_LCR_8N1 EQU %11000000 ; 8n1 Serial Mode @@ -49,7 +55,7 @@ UARTF_LCR_SPR EQU %00000100 ; Stick Parity UARTF_LCR_BRK EQU %00000010 ; Set Break UARTF_LCR_DLAB EQU %00000001 ; Divisor Latch Access Bit -; UART Flags for Modem Control Register: +; UART Flags for MODEM Control Register: UARTF_MCR_DTR EQU %10000000 ; Data Terminal Ready UARTF_MCR_RTS EQU %01000000 ; Enabling Request to Send UARTF_MCR_OUT1 EQU %00100000 ; Out 1 @@ -66,7 +72,7 @@ UARTF_LSR_THRE EQU %00000100 ; Transmitter Holding Register UARTF_LSR_TEMT EQU %00000010 ; Transmitter Empty UARTF_LSR_FIFO EQU %00000001 ; Error in RCVR FIFO -; UART Flags for Modem Status Register: +; UART Flags for MODEM Status Register: UARTF_MSR_DCTS EQU %10000000 ; Delta Clear to Send UARTF_MSR_DDSR EQU %01000000 ; Delta Data Set Ready UARTF_MSR_TERI EQU %00100000 ; Trailing Edge Ring Indicator From d787e63624f156a1eeaba840d653ebc6614b896c Mon Sep 17 00:00:00 2001 From: Gale Faraday Date: Thu, 5 Dec 2024 14:50:20 -0600 Subject: [PATCH 11/13] feat(hardware.inc): Added flags for IIR --- code/boot/src/hardware.inc | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/code/boot/src/hardware.inc b/code/boot/src/hardware.inc index 7eb25b7..4246f25 100644 --- a/code/boot/src/hardware.inc +++ b/code/boot/src/hardware.inc @@ -38,7 +38,7 @@ UART_LSR EQU UART_BASE + 5 ; Line Status Register UART_MSR EQU UART_BASE + 6 ; MODEM Status Register UART_SCR EQU UART_BASE + 7 ; Scratch Register (Not for control just spare RAM) -; TODO: Flags for IIR, FCR +; TODO: Flags for FCR ; UART Flags for Interrupt Enable Register: UARTF_IER_ERBFI EQU %10000000 ; Enable Received Data Available Interrupt @@ -46,6 +46,11 @@ UARTF_IER_ETBEI EQU %01000000 ; Enable Transmitter Holding Register Empty Interr UARTF_IER_ELSI EQU %00100000 ; Enable Receiver Line Status Interrupt UARTF_IER_EDSSI EQU %00010000 ; Enable MODEM Status Interrupt +; UART Flags for Interrupt Ident Register: +UARTF_IIR_INP EQU %10000000 ; Reset if Interrupt Pending; 'INP' = Interrupt Not Pending +UARTF_IIR_IIDM EQU %01110000 ; Interrupt ID Mask +UARTF_IIR_FEM EQU %00000011 ; FIFOs Enabled Mask + ; UART Flags for Line Control Register: UARTF_LCR_8N1 EQU %11000000 ; 8n1 Serial Mode UARTF_LCR_STB EQU %00100000 ; Stop Bits From 6605f1300340adb4d5f8ae211b986ff63cc1950c Mon Sep 17 00:00:00 2001 From: Gale Faraday Date: Thu, 5 Dec 2024 14:54:43 -0600 Subject: [PATCH 12/13] feat(hardware.inc): Added flags for FCR --- code/boot/src/hardware.inc | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/code/boot/src/hardware.inc b/code/boot/src/hardware.inc index 4246f25..8871e94 100644 --- a/code/boot/src/hardware.inc +++ b/code/boot/src/hardware.inc @@ -38,14 +38,20 @@ UART_LSR EQU UART_BASE + 5 ; Line Status Register UART_MSR EQU UART_BASE + 6 ; MODEM Status Register UART_SCR EQU UART_BASE + 7 ; Scratch Register (Not for control just spare RAM) -; TODO: Flags for FCR - ; UART Flags for Interrupt Enable Register: UARTF_IER_ERBFI EQU %10000000 ; Enable Received Data Available Interrupt UARTF_IER_ETBEI EQU %01000000 ; Enable Transmitter Holding Register Empty Interrupt UARTF_IER_ELSI EQU %00100000 ; Enable Receiver Line Status Interrupt UARTF_IER_EDSSI EQU %00010000 ; Enable MODEM Status Interrupt +; UART Flags for FIFO Control Register: +UARTF_FCR_FE EQU %10000000 ; FIFO Enabled +UARTF_FCR_RFR EQU %01000000 ; RCVR FIFO Reset +UARTF_FCR_XFR EQU %00100000 ; XMIT FIFO Reset +UARTF_FCR_DMS EQU %00010000 ; DMA Mode Select +UARTF_FCR_RTL EQU %00000010 ; RCVR Trigger (LSB) +UARTF_FCR_RTM EQU %00000001 ; RCVR Trigger (MSB) + ; UART Flags for Interrupt Ident Register: UARTF_IIR_INP EQU %10000000 ; Reset if Interrupt Pending; 'INP' = Interrupt Not Pending UARTF_IIR_IIDM EQU %01110000 ; Interrupt ID Mask From 16c2d2bc624cfd055c784f2f9c1088b1abf2eb45 Mon Sep 17 00:00:00 2001 From: Amber Date: Thu, 5 Dec 2024 16:44:02 -0500 Subject: [PATCH 13/13] fix: register name, comment spacing --- code/boot/src/boot.s | 2 +- code/boot/src/hardware.inc | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/code/boot/src/boot.s b/code/boot/src/boot.s index 6dfac52..e09b5d5 100644 --- a/code/boot/src/boot.s +++ b/code/boot/src/boot.s @@ -27,7 +27,7 @@ RESET lda #%01000000 ; Enable RTS sta UART_MCR - lda 'H ; send 'H' + lda 'H ; send 'H' sta UART_BUFR WAIT diff --git a/code/boot/src/hardware.inc b/code/boot/src/hardware.inc index 8871e94..0049d02 100644 --- a/code/boot/src/hardware.inc +++ b/code/boot/src/hardware.inc @@ -58,7 +58,7 @@ UARTF_IIR_IIDM EQU %01110000 ; Interrupt ID Mask UARTF_IIR_FEM EQU %00000011 ; FIFOs Enabled Mask ; UART Flags for Line Control Register: -UARTF_LCR_8N1 EQU %11000000 ; 8n1 Serial Mode +UARTF_LCR_WLS EQU %11000000 ; Word Length Select Bits UARTF_LCR_STB EQU %00100000 ; Stop Bits UARTF_LCR_PEN EQU %00010000 ; Parity Enable UARTF_LCR_EPS EQU %00001000 ; Even Parity Select