forked from amberisvibin/chibi-pc09
121 lines
2.9 KiB
ArmAsm
121 lines
2.9 KiB
ArmAsm
; CHIBI PC-09 Prototype #1 Boot ROM -- Hardware Initialization and Reset Vecs
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; Copyright (c) 2024 Amber Zeller, Gale Faraday
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; Licensed under MIT
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INCLUDE "src/hardware.inc"
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; Hardware Initialization Routines
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;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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SECTION "Reset"
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ORG ROM_BASE
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RESET
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; 8n1 Serial Enable DLAB
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lda #(UARTF_LCR_WLS | UARTF_LCR_DLAB)
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sta UART_LCR
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; REVIEW: Potential endianness hiccough here
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ldd #$0C00 ; Set divisor to 12 (9600 baud)
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sta UART_DLM
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stb UART_DLL
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lda #(UARTF_LCR_WLS) ; 8n1 serial, disable DLAB
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sta UART_LCR
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lda #(UARTF_MCR_RTS) ; Enable Request-to-Send
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sta UART_MCR
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lda 'H ; send 'H'
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sta UART_BUFR
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WAIT
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sync ; Wait for interrupts
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nop
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bra WAIT
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SECTION "Serial"
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; Writes a char to the UART in non FIFO mode, preserves A.
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; @param b: char to write
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OUTCHAR
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pshs a ; Preserve A
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1
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lda UART_LSR ; if LSR.THRE == 1 then write
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anda UARTF_LSR_THRE
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bne 1B ; Loop if UART not ready yet
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stb UART_BUFR ; Write char
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puls a ; Restore A
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rts
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; Writes a null terminated string to the UART in non FIFO mode, clobbers A and
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; B.
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; @param x: null terminated string start address.
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OUTSTR
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ldb x ; Get the next value from X
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cmpb #$00 ; Make sure that mother is non-null
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beq 2F
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leax 1,x ; Increment X for our next char
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1 ; Loop point for UART waiting
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lda UART_LSR ; Wait for UART to be ready
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anda UARTF_LSR_THRE
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bne 1B
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stb UART_BUFR ; Actually do our write
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bra OUTSTR ; Reset for the next char
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2 ; Jump point for end of routine
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rts
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SECTION "Memtest"
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; RAM testing routine. Ported to 6809 from 6800, based on source for ROBIT-2 for
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; MIKBUG.
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RAMTEST
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ldx #SRAM_BASE ; Store 1 in memory
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lda #1
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sta 0,x
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cmpa 0,x
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bne 1F
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1 ; Loop point for next
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asla ; Shift A and [X] left
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asl 0,x
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cmpa 0,x
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bne 1F
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cmpa #$80 ; Only test up to $80
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bne 1B
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bra 2F
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1 ; Write out error indicator
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ldb #'X
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jsr OUTCHAR
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bra 3F ; Branch to finish
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2
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cmpx #$60FF ; Compare X to end of RAM
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beq 3F ; Finish if done, else try next address
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leax 1,x
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bra RAMTEST
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3
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ldb #'P
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jsr OUTCHAR
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rts
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; Interrupt and Reset Vectors
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;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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SECTION "Vectors"
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ORG VECS_BASE
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VECTORS
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fdb $0000 ; Reserved
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fdb $0000 ; SWI3
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fdb $0000 ; SWI2
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fdb $0000 ; FIRQ
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fdb $0000 ; IRQ
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fdb $0000 ; SWI
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fdb $0000 ; NMI
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fdb RESET ; Reset
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