51 Commits

Author SHA1 Message Date
cc8a9fc95f feat(boot): new stack initialization routine 2025-09-02 16:46:45 -05:00
a0427ad949 Update bootloader README and clean up makefile 2025-09-02 15:46:55 -05:00
0845370c43 Adjusted code/boot/makefile to remove map.txt when make clean is run 2025-09-02 13:36:24 -04:00
347b6fa236 Merge pull request 'Migration to LWTOOLS' (#2) from gfaraday/chibi-pc09:main into main 2025-09-02 13:32:31 -04:00
677b3cb02d feat: modularized with lwtools build system 2025-08-31 14:42:14 -05:00
c67176e99a feat\!: migrate to LWTOOLS build system 2025-08-31 13:44:00 -05:00
9c668967d5 Merge pull request 'Merge memory test and serial output routines' (#1) from gfaraday/chibi-pc09:main into main
Reviewed-on: amberisvibin/chibi-pc09#1
2025-08-22 11:36:24 -04:00
53c6c7fd78 fix boot firmware README 2025-08-22 08:14:17 -04:00
08b85a186e remove old data from docs/ 2025-08-21 15:59:04 -04:00
9f28e315b7 clean up datasheets/ and remove outdated files 2025-08-21 15:57:33 -04:00
69836aa24b new pcb cleanup 2025-08-21 15:44:32 -04:00
5bd4c7ae15 Merge pull request 'Integrate port of ROBIT-2' (#2) from memtest into main
Reviewed-on: #2
2025-08-20 18:39:21 -04:00
9a4f9fb6dd Merge branch 'memtest' of https://gitea.ambersplace.net/gfaraday/chibi-pc09 into memtest 2025-08-20 17:36:18 -05:00
3835594548 refactor(memtest): refactored the port of ROBIT-2 2025-08-20 17:30:35 -05:00
f6642860a5 feat: ported ROBIT-2 for MIKBUG to CHIBI PC-09 2025-08-20 17:30:35 -05:00
9dc46c16ee Merge pull request 'serial' (#1) from serial into main
Reviewed-on: #1
2025-08-20 18:29:54 -04:00
4e6cdc8834 new pcb rev, fixes reset switch error 2025-08-18 08:34:37 -04:00
62a7ccc35a Add The 6309 Book 2025-08-18 07:56:03 -04:00
9a72eda0e5 add badge for gitea 2025-08-01 12:41:33 -04:00
0eb5b2ba89 update readme to reflect changes 2025-08-01 07:59:28 -04:00
6e89d26f6b docs: add 74hc670 datasheet, potential replacement for 74ls612 2024-12-16 09:35:04 -05:00
d2c5118ba2 refactor(memtest): refactored the port of ROBIT-2 2024-12-11 06:49:44 -06:00
a642e05c2c feat: ported ROBIT-2 for MIKBUG to CHIBI PC-09 2024-12-11 06:35:11 -06:00
9edc255412 style: caps in comment fix 2024-12-11 05:30:33 -06:00
971dc1d719 feat: new serial functions 2024-12-07 10:30:15 -06:00
1237cc89eb chore: using aliases from hardware.inc and optimized divisor setup 2024-12-07 06:55:22 -06:00
Amber
808f868344 Merge pull request #12 from amberisvibin/hardware.inc
Setup hardware.inc
2024-12-05 20:59:14 -05:00
16c2d2bc62 fix: register name, comment spacing 2024-12-05 16:44:02 -05:00
6605f13003 feat(hardware.inc): Added flags for FCR 2024-12-05 14:54:43 -06:00
d787e63624 feat(hardware.inc): Added flags for IIR 2024-12-05 14:50:20 -06:00
7d03e97d94 feat(hardware.inc): added flags for IER and changed 'Modem'->'MODEM' 2024-12-05 14:45:45 -06:00
b3ebe917a9 feat(hardware.inc): added flags for MSR. 2024-12-05 12:28:58 -06:00
1294ac41d1 feat(hardware.inc): added flags for LCR, MCR, and LSR. 2024-12-05 12:23:31 -06:00
d1cbc09e99 fix: fixed immediate values 2024-11-29 10:10:48 -06:00
83029f6617 chore: added flag for 8n1 serial 2024-11-29 10:10:23 -06:00
e66019f9ac chore: added .inc to editorconfig rules. 2024-11-29 10:09:46 -06:00
088f5d838c fix: added vim ft=asm to inc file. 2024-11-29 09:30:00 -06:00
0b0fd1f83e chore: added SRAM_BASE to hardware.inc. 2024-11-28 23:16:45 -06:00
10491c65e7 style: removed pointless newline 2024-11-28 22:55:57 -06:00
616e95bb0a chore: added ROM_BASE and VECS_BASE to hardware.inc 2024-11-28 22:54:00 -06:00
10c9491164 fix: now tracking incs in makefile. 2024-11-28 11:17:23 -06:00
ad66da0840 style: moved comments to the side 2024-11-28 11:16:58 -06:00
8c2f330cd7 fix: broken whitespace expected by asm6809. 2024-11-28 11:10:30 -06:00
91286a143d refactor: made preparations for hardware.inc. 2024-11-28 11:07:22 -06:00
89218accd0 feat: add hardware.inc 2024-11-28 11:05:23 -06:00
4a50a80e1f style: prettier math (thx asm6809), add MIT license to boot.s, remove stray ( 2024-11-22 10:17:26 -05:00
3e4e0487a3 chore: organize pcb files 2024-11-22 09:59:27 -05:00
Amber
ce30f0c1f0 docs: update directories in README 2024-11-22 09:45:10 -05:00
2a3732ce6a chore: remove old docs, clean up font stuff 2024-11-22 09:42:05 -05:00
bbe4799903 docs: update code README to reflect changes and update main README with new update 2024-11-22 09:30:21 -05:00
d0ccf52bb3 fix: use a version of assist09 that is compatible with asm6809 2024-11-22 09:22:54 -05:00
313 changed files with 49731 additions and 98076 deletions

2
.gitignore vendored
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@@ -1,3 +1,3 @@
widgets.qss
*.lck
prototype-1-backups/

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@@ -1,17 +1,19 @@
# chibi pc-09
![GitHub last commit](https://img.shields.io/github/last-commit/amberisvibin/chibi-pc80)
![Gitea last commit](https://img.shields.io/gitea/last-commit/amberisvibin/chibi-pc09?gitea_url=https%3A%2F%2Fgitea.ambersplace.net&style=for-the-badge&label=Last%20Gitea%20Commit)
![GitHub last commit](https://img.shields.io/github/last-commit/amberisvibin/chibi-pc09?style=for-the-badge&label=Last%20Github%20Commit)
## Description
The PC-09 will be a 6309 based microcomputer with a 74LS612 MMU, uPD72020 graphics, PS/2 keyboard and mouse input, and a capable UART.
The PC-09 will be a 6309 based microcomputer with an MMU using 74HC670 register files and dual 16550 UARTs. The plan is to eventually add uPD7220 graphics and PS/2 mouse and keyboard.
The MMU will allow up to 2 megabytes of I/O to be paged into the address space. Pages are 4k. System storage will be paged into the address space as well, as it will be either EEPROM or flash.
The two 74HC670s will take the top 4 bits of the address bus and expand them to 8 bits, turning the 16 bit cpu address space into a 20 bit address space capable of addressing 1MB of memory. Memory pages are 4KB. Being a register file, any page can be mapped to any slot, allowing complex memory management schemes.
The uPD72020 is a very advanced graphics chip for it's time, capable of accelerated drawing of lines, shapes, fills, and characters. It can be coerced into outputting a VGA signal at 640x480 and *maybe* 800x600.
The 16550 UART is capable of interrupt driven operation with FIFOs, allowing for characters to be processed in batches rather than individually, minimizing task switch delays. They also support hardware flow control, and some versions can automatically assert RTS when the FIFO is nearing full.
Keyboard and mouse will be handled by the VIA VT82C42. It is an Intel 8242 compatible controller capable of both PS/2 keyboard and mouse. It's interface is relatively simple, which makes connection easy. It relies on interrupts, so an interrupt system will be required.
The uPD7220 graphics are very powerful, allowing 16 colors at 640x480, but it is a complex chip to get working. It will be left for a later date.
To avoid the infamous 65C22 bug, the system will use the 16550 UART from the PC ecosystem. It is *relatively* easy to interface this to a 6800 style bus. It has more features than a 65C22 as well. As configured, it will be stable up to 38,400 baud.
The solution for PS/2 keyboard and mouse have not yet been decided.
## Progress
@@ -19,6 +21,10 @@ I had started wiring together a board for prototyping, but it was destroyed in h
Prototype 1 is currently in progress. It will be a much simpler system. It will have no MMU, just the CPU, some RAM, some ROM, and the UART.
The PCB and parts for Prototype #1 have been ordered, and assembly will begin soon. Initial test code is now available in the code/ directory.
Assembly is in progress.
## License
This project is licensed under the MIT license. This applies to both the hardware (schematics, bill of materials, pcb layouts) and documentation. This does *not* apply to the datasheets/ directory, the books/ directory or code/assist09/assist09.asm. Those files belong to their respective copyright holders.
This project is licensed under the MIT license. This applies to both the hardware (schematics, bill of materials, pcb layouts) and documentation. This does *not* apply to the datasheets/ directory or code/assist09/. Those files belong to their respective copyright holders.

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@@ -1,13 +1,7 @@
# Code
## assist09/
These are the sources for the boot code for Prototype #1. ASSIST09 will eventually be integrated.
assist09.asm is the original motorola version, and relies on the as9 assembler found [here](http://home.hccnet.nl/a.w.m.van.der.horst/m6809.html).
The version of ASSIST09 that is being used has been modified for asm6809 by the [MECB](https://github.com/DigicoolThings/MECB) project and is available [here](https://github.com/DigicoolThings/MECB/blob/main/MECB_6809_CPU/ASSIST09/src/ASSIST09_Original_ASM6809.asm).
assemble.sh will assemble assist09.asm to an s19 file and use gnu binutils objcopy to turn that into a bin file.
## boot/
the boot code for prototype 1, uses the lwtools assembler.
assemble.sh will assemble boot.s to an s19 file and use gnu binutils objcopy to turn that into a bin file.
Information for building the boot code is under boot/README.md.

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@@ -68,33 +68,33 @@ NUMFUN EQU 11 ; NUMBER OF AVAILABLE FUNCTIONS
* THEY ARE EQUIVALENT TO OFFSETS IN THE TABLE.
* RELATIVE POSITIONING MUST BE MAINTAINED
.AVTBL EQU 0 ; ADDRESS OF VECTOR TABLE
.CMDL1 EQU 2 ; FIRST COMMAND LIST
.RSVD EQU 4 ; RESERVED HARDWARE VECTOR
.SWI3 EQU 6 ; SWI3 ROUTINE
.SWI2 EQU 8 ; SWI2 ROUTINE
.FIRQ EQU 10 ; FIRQ ROUTINE
.IRQ EQU 12 ; IRQ ROUTINE
.SWI EQU 14 ; SWI ROUTINE
.NMI EQU 16 ; NMI ROUTINE
.RESET EQU 18 ; RESET ROUTINE
.CION EQU 20 ; CONSOLE ON
.CIDTA EQU 22 ; CONSOLE INPUT DATA
.CIOFF EQU 24 ; CONSOLE INPUT OFF
.COON EQU 26 ; CONSOLE OUTPUT ON
.CODTA EQU 28 ; CONSOLE OUTPUT DATA
.COOFF EQU 30 ; CONSOLE OUTPUT OFF
.HSDTA EQU 32 ; HIGH SPEED PRINTDATA
.BSON EQU 34 ; PUNCH/LOAD ON
.BSDTA EQU 36 ; PUNCH/LOAD DATA
.BSOFF EQU 38 ; PUNCH/LOAD OFF
.PAUSE EQU 40 ; TASK PAUSE ROUTINE
.EXPAN EQU 42 ; EXPRESSION ANALYZER
.CMDL2 EQU 44 ; SECOND COMMAND LIST
.ACIA EQU 46 ; ACIA ADDRESS
.PAD EQU 48 ; CHARACTER PAD AND NEW LINE PAD
.ECHO EQU 50 ; ECHO/LOAD AND NULL BKPT FLAG
.PTM EQU 52 ; PTM ADDRESS
_AVTBL EQU 0 ; ADDRESS OF VECTOR TABLE
_CMDL1 EQU 2 ; FIRST COMMAND LIST
_RSVD EQU 4 ; RESERVED HARDWARE VECTOR
_SWI3 EQU 6 ; SWI3 ROUTINE
_SWI2 EQU 8 ; SWI2 ROUTINE
_FIRQ EQU 10 ; FIRQ ROUTINE
_IRQ EQU 12 ; IRQ ROUTINE
_SWI EQU 14 ; SWI ROUTINE
_NMI EQU 16 ; NMI ROUTINE
_RESET EQU 18 ; RESET ROUTINE
_CION EQU 20 ; CONSOLE ON
_CIDTA EQU 22 ; CONSOLE INPUT DATA
_CIOFF EQU 24 ; CONSOLE INPUT OFF
_COON EQU 26 ; CONSOLE OUTPUT ON
_CODTA EQU 28 ; CONSOLE OUTPUT DATA
_COOFF EQU 30 ; CONSOLE OUTPUT OFF
_HSDTA EQU 32 ; HIGH SPEED PRINTDATA
_BSON EQU 34 ; PUNCH/LOAD ON
_BSDTA EQU 36 ; PUNCH/LOAD DATA
_BSOFF EQU 38 ; PUNCH/LOAD OFF
_PAUSE EQU 40 ; TASK PAUSE ROUTINE
_EXPAN EQU 42 ; EXPRESSION ANALYZER
_CMDL2 EQU 44 ; SECOND COMMAND LIST
_ACIA EQU 46 ; ACIA ADDRESS
_PAD EQU 48 ; CHARACTER PAD AND NEW LINE PAD
_ECHO EQU 50 ; ECHO/LOAD AND NULL BKPT FLAG
_PTM EQU 52 ; PTM ADDRESS
NUMVTR EQU 52/2+1 ; NUMBER OF VECTORS
HIVTR EQU 52 ; HIGHEST VECTOR OFFSET
@@ -108,7 +108,7 @@ HIVTR EQU 52 ; HIGHEST VECTOR OFFSET
* DEFINED HEREIN.
******************************************
WORKPG EQU ROMBEG+RAMOFS ; SETUP DIRECT PAGE ADDRESS
* SETDP =WORKPG ; NOTIFY ASSEMBLER
SETDP WORKPG!>8 ; NOTIFY ASSEMBLER
ORG WORKPG+256 ; READY PAGE DEFINITIONS
* THE FOLLOWING THRU BKPTOP MUST RESIDE IN THIS ORDER
@@ -341,12 +341,12 @@ SIGNON FCC /ASSIST09/ ; SIGNON EYE-CATCHER
ZMONTR STS <RSTACK ; SAVE FOR BAD STACK RECOVERY
TST 1,S ; ? INIT CONSOLE AND SEND MSG
BNE ZMONT2 ; BRANCH IF NOT
JSR [VECTAB+.CION,PCR] ; READY CONSOLE INPUT
JSR [VECTAB+.COON,PCR] ; READY CONSOLE OUTPUT
JSR [VECTAB+_CION,PCR] ; READY CONSOLE INPUT
JSR [VECTAB+_COON,PCR] ; READY CONSOLE OUTPUT
LEAX SIGNON,PCR ; READY SIGNON EYE-CATCHER
SWI ; PERFORM
FCB PDATA ; PRINT STRING
ZMONT2 LDX <VECTAB+.PTM ; LOAD PTM ADDRESS
ZMONT2 LDX <VECTAB+_PTM ; LOAD PTM ADDRESS
BEQ CMD ; BRANCH IF NOT TO USE A PTM
CLR PTMTM1-PTM,X ; SET LATCH TO CLEAR RESET
CLR PTMTM1+1-PTM,X ; AND SET GATE HIGH
@@ -423,10 +423,10 @@ CMD3 LBSR READ ; OBTAIN NEXT CHARACTER
* GOT COMMAND, NOW SEARCH TABLES
CMDGOT SUBA #CR ; SET ZERO IF CARRIAGE RETURN
STA -3,U ; SETUP FLAG
LDX <VECTAB+.CMDL1 ; START WITH FIRST CMD LIST
LDX <VECTAB+_CMDL1 ; START WITH FIRST CMD LIST
CMDSCH LDB ,X+ ; LOAD ENTRY LENGTH
BPL CMDSME ; BRANCH IF NOT LIST END
LDX <VECTAB+.CMDL2 ; NOW TO SECOND CMD LITS
LDX <VECTAB+_CMDL2 ; NOW TO SECOND CMD LITS
INCB ; ? TO CONTINUE TO DEFAULT LIST
BEQ CMDSCH ; BRANCH IF SO
CMDBAD LDS <PSTACK ; RESTORE STACK
@@ -562,7 +562,7 @@ ZOUTHX ADDA #$90 ; PREPARE A-F ADJUST
DAA ; ADJUST
ADCA #$40 ; PREPARE CHARACTER BITS
DAA ; ADJUST
SEND JMP [VECTAB+.CODTA,PCR] ; SEND TO OUT HANDLER
SEND JMP [VECTAB+_CODTA,PCR] ; SEND TO OUT HANDLER
ZOT4HS BSR ZOUT2H ; CONVERT FIRST BYTE
ZOT2HS BSR ZOUT2H ; CONVERT BYTE TO HEX
@@ -588,7 +588,7 @@ ZSPACE LDA #' ; LOAD BLANK
ZVSWTH LDA 1,S ; LOAD REQUESTERS A
CMPA #HIVTR ; ? SUB-CODE TOO HIGH
BHI ZOTCH3 ; IGNORE CALL IF SO
LDY <VECTAB+.AVTBL ; LOAD VECTOR TABLE ADDRESS
LDY <VECTAB+_AVTBL ; LOAD VECTOR TABLE ADDRESS
LDU A,Y ; U=OLD ENTRY
STU 4,S ; RETURN OLD VALUE TO CALLERS X
STX -2,S ; ? X=0
@@ -619,7 +619,7 @@ ZINCH BSR XQCIDT ; CALL INPUT DATA APPENDAGE
BNE ZIN2 ; NO, TEST ECHO BYTE
LDA #LF ; LOAD LINE FEED
BSR SEND ; ALWAYS ECHO LINE FEED
ZIN2 TST <VECTAB+.ECHO ; ? ECHO DESIRED
ZIN2 TST <VECTAB+_ECHO ; ? ECHO DESIRED
BNE ZOTCH3 ; NO, RETURN
* FALL THROUGH TO OUTCH
************************************************
@@ -718,8 +718,8 @@ CHKWT BSR XQPAUS ; PAUSE FOR A MOMENT
RTS ; AND RETURN
* SAVE MEMORY WITH JUMPS
XQPAUS JMP [VECTAB+.PAUSE,PCR] ; TO PAUSE ROUTINE
XQCIDT JSR [VECTAB+.CIDTA,PCR] ; TO INPUT ROUTINE
XQPAUS JMP [VECTAB+_PAUSE,PCR] ; TO PAUSE ROUTINE
XQCIDT JSR [VECTAB+_CIDTA,PCR] ; TO INPUT ROUTINE
ANDA #$7F ; STRIP PARITY
RTS ; RETURN TO CALLER
@@ -821,7 +821,7 @@ FIRQR EQU RTI ; IMMEDIATE RETURN
* OUTPUT: C=0 IF NO DATA READY, C=1 A=CHARACTER
* U VOLATILE
CIDTA LDU <VECTAB+.ACIA ; LOAD ACIA ADDRESS
CIDTA LDU <VECTAB+_ACIA ; LOAD ACIA ADDRESS
LDA ,U ; LOAD STATUS REGISTER
LSRA ; TEST RECEIVER REGISTER FLAG
BCC CIRTN ; RETURN IF NOTHING
@@ -833,7 +833,7 @@ CIRTN RTS ; RETURN TO CALLER
* A,X VOLATILE
CION EQU *
COON LDA #3 ; RESET ACIA CODE
LDX <VECTAB+.ACIA ; LOAD ACIA ADDRESS
LDX <VECTAB+_ACIA ; LOAD ACIA ADDRESS
STA ,X ; STORE INTO STATUS REGISTER
LDA #$51 ; SET CONTROL
STA ,X ; REGISTER UP
@@ -849,14 +849,14 @@ COOFF EQU RTS ; CONSOLE OUTPUT OFF
* ALL REGISTERS TRANSPARENT
CODTA PSHS U,D,CC ; SAVE REGISTERS,WORK BYTE
LDU <VECTAB+.ACIA ; ADDRESS ACIA
LDU <VECTAB+_ACIA ; ADDRESS ACIA
BSR CODTAO ; CALL OUTPUT CHAR SUBROUTINE
CMPA #DLE ; ? DATA LINE ESCAPE
BEQ CODTRT ; YES, RETURN
LDB <VECTAB+.PAD ; DEFAULT TO CHAR PAD COUNT
LDB <VECTAB+_PAD ; DEFAULT TO CHAR PAD COUNT
CMPA #CR ; ? CR
BNE CODTPD ; BRANCH NO
LDB <VECTAB+.PAD+1 ; LOAD NEW LINE PAD COUNT
LDB <VECTAB+_PAD+1 ; LOAD NEW LINE PAD COUNT
CODTPD CLRA ; CREATE NULL
STB ,S ; SAVE COUNT
FCB SKIP2 ; ENTER LOOP
@@ -866,10 +866,10 @@ CODTLP BSR CODTAO ; SEND NULL
CODTRT PULS PC,U,D,CC ; RESTORE REGISTERS AND RETURN
CODTAD LBSR XQPAUS ; TEMPORARY GIVE UP CONTROL
CODTAO LDB 1,U ; LOAD ACIA CONTROL REGISTER
BITB #$02 ; ? TX REGISTER CLEAR >LSAB FIXME
BNE CODTAD ; RELEASE CONTROL IF NOT
STA ,U ; STORE INTO DATA REGISTER
CODTAO LDB ,U ; LOAD ACIA CONTROL REGISTER
BITB #$02 ; ? TX REGISTER CLEAR
BEQ CODTAD ; RELEASE CONTROL IF NOT
STA 1,U ; STORE INTO DATA REGISTER
RTS ; RETURN TO CALLER
*E
@@ -975,15 +975,15 @@ BYTHEX SWI ; GET NEXT HEX
* S+1=FRAME COUNT/CHECKSUM
* S+0=BYTE COUNT
BSDPUN LDU <VECTAB+.PAD ; LOAD PADDING VALUES
BSDPUN LDU <VECTAB+_PAD ; LOAD PADDING VALUES
LDX 4,S ; X=FROM ADDRESS
PSHS U,X,D ; CREATE STACK WORK AREA
LDD #24 ; SET A=0, B=24
STB <VECTAB+.PAD ; SETUP 24 CHARACTER PADS
STB <VECTAB+_PAD ; SETUP 24 CHARACTER PADS
SWI ; SEND NULLS OUT
FCB OUTCH ; FUNCTION
LDB #4 ; SETUP NEW LINE PAD TO 4
STD <VECTAB+.PAD ; SETUP PUNCH PADDING
STD <VECTAB+_PAD ; SETUP PUNCH PADDING
* CALCULATE SIZE
BSPGO LDD 8,S ; LOAD TO
SUBD 2,S ; MINUS FROM=LENGTH
@@ -1024,14 +1024,14 @@ BSPMRE BSR BSPUN2 ; SEND OUT NEXT BYTE
SWI ; SEND OUT STRING
FCB PDATA ; FUNCTION
LDD 4,S ; RECOVER PAD COUNTS
STD <VECTAB+.PAD ; RESTORE
STD <VECTAB+_PAD ; RESTORE
CLRA ; SET Z=1 FOR OK RETURN
PULS PC,U,X,D ; RETURN WITH OK CODE
BSPUN2 ADDB ,X ; ADD TO CHECKSUM
BSPUNC LBRA ZOUT2H ; SEND OUT AS HEX AND RETURN
BSPSTR FCB 'S,'1,EOT ; CR,LF,NULLS,S,1
BSPEOF FCC /S9030000FC/ ; EOF STRING
BSPSTR FCB 'S,'1,EOT ; CR,LF,NULLS,S,1
BSPEOF FCC /S9030000FC/ ; EOF STRING
FCB CR,LF,EOT
* HSDTA - HIGH SPEED PRINT MEMORY
@@ -1084,7 +1084,7 @@ HSHCOK SWI ; SEND CHARACTER
FCB OUTCH ; FUNCTION
DECB ; ? DONE
BNE HSHCHR ; BRANCH NO
CPX 2,S ; ? PAST LAST ADDRESS
CMPX 2,S ; ? PAST LAST ADDRESS
BHS HSDRTN ; QUIT IF SO
STX 4,S ; UPDATE FROM ADDRESS
LDA 5,S ; LOAD LOW BYTE ADDRESS
@@ -1224,7 +1224,7 @@ BLDNNB CLRA ; NO DYNAMIC DELIMITER
* BUILD WITH LEADING BLANKS
BLDNUM LDA #' ; ALLOW LEADING BLANKS
STA <DELIM ; STORE AS DELIMITER
JMP [VECTAB+.EXPAN,PCR] ; TO EXP ANALYZER
JMP [VECTAB+_EXPAN,PCR] ; TO EXP ANALYZER
* THIS IS THE DEFAULT SINGLE ROM ANALYZER. WE ACCEPT:
* 1) HEX INPUT
* 2) 'M' FOR LAST MEMORY EXAMINE ADDRESS
@@ -1491,7 +1491,7 @@ CDISPS PSHS Y,X ; SETUP PARAMETERS FOR HSDATA
CMPD 2,S ; ? WAS IT COUNT
BLS CDCNT ; BRANCH YES
STD ,S ; STORE HIGH ADDRESS
CDCNT JSR [VECTAB+.HSDTA,PCR] ; CALL PRINT ROUTINE
CDCNT JSR [VECTAB+_HSDTA,PCR] ; CALL PRINT ROUTINE
PULS PC,U,Y ; CLEAN STACK AND END COMMAND
* OBTAIN NUMBER - ABORT IF NONE
@@ -1513,10 +1513,10 @@ CPUNCH BSR CDNUM ; OBTAIN START ADDRESS
BSR CDNUM ; OBTAIN END ADDRESS
CLR ,-S ; SETUP PUNCH FUNCTION CODE
PSHS Y,D ; STORE VALUES ON STACK
CCALBS JSR [VECTAB+.BSON,PCR] ; INITIALIZE HANDLER
JSR [VECTAB+.BSDTA,PCR] ; PERFORM FUNCTION
CCALBS JSR [VECTAB+_BSON,PCR] ; INITIALIZE HANDLER
JSR [VECTAB+_BSDTA,PCR] ; PERFORM FUNCTION
PSHS CC ; SAVE RETURN CODE
JSR [VECTAB+.BSOFF,PCR] ; TURN OFF HANDLER
JSR [VECTAB+_BSOFF,PCR] ; TURN OFF HANDLER
PULS CC ; OBTAIN CONDITION CODE SAVED
BNE CDBADN ; BRANCH IF ERROR
PULS PC,Y,X,A ; RETURN FROM COMMAND
@@ -1546,14 +1546,14 @@ CTRACE BSR CDNUM ; OBTAIN TRACE COUNT
CDOT LEAS 2,S ; RID COMMAND RETURN FROM STACK
CTRCE3 LDU [10,S] ; LOAD OPCODE TO EXECUTE
STU <LASTOP ; STORE FOR TRACE INTERRUPT
LDU <VECTAB+.PTM ; LOAD PTM ADDRESS
LDU <VECTAB+_PTM ; LOAD PTM ADDRESS
LDD #$0701 ; 7,1 CYCLES DOWN+CYCLES UP
STD PTMTM1-PTM,U ; START NMI TIMEOUT
RTI ; RETURN FOR ONE INSTRUCTION
*************NULLS - SET NEW LINE AND CHAR PADDING
CNULLS BSR CDNUM ; OBTAIN NEW LINE PAD
STD <VECTAB+.PAD ; RESET VALUES
STD <VECTAB+_PAD ; RESET VALUES
RTS ; END COMMAND
******************STLEVEL - SET STACK TRACE LEVEL
@@ -1713,13 +1713,13 @@ CONV2
****************************************************
* DEFAULT INTERRUPT TRANSFERS *
****************************************************
RSRVD JMP [VECTAB+.RSVD,PCR] ; RESERVED VECTOR
SWI3 JMP [VECTAB+.SWI3,PCR] ; SWI3 VECTOR
SWI2 JMP [VECTAB+.SWI2,PCR] ; SWI2 VECTOR
FIRQ JMP [VECTAB+.FIRQ,PCR] ; FIRQ VECTOR
IRQ JMP [VECTAB+.IRQ,PCR] ; IRQ VECTOR
SWI JMP [VECTAB+.SWI,PCR] ; SWI VECTOR
NMI JMP [VECTAB+.NMI,PCR] ; NMI VECTOR
RSRVD JMP [VECTAB+_RSVD,PCR] ; RESERVED VECTOR
SWI3 JMP [VECTAB+_SWI3,PCR] ; SWI3 VECTOR
SWI2 JMP [VECTAB+_SWI2,PCR] ; SWI2 VECTOR
FIRQ JMP [VECTAB+_FIRQ,PCR] ; FIRQ VECTOR
IRQ JMP [VECTAB+_IRQ,PCR] ; IRQ VECTOR
SWI JMP [VECTAB+_SWI,PCR] ; SWI VECTOR
NMI JMP [VECTAB+_NMI,PCR] ; NMI VECTOR
******************************************************
* ASSIST09 HARDWARE VECTOR TABLE

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@@ -1,2 +0,0 @@
as9 assist09.asm -l s19
objcopy --input-target=srec --output-target=binary assist09.s19 assist09.bin

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@@ -8,7 +8,7 @@ charset = utf-8
trim_trailing_whitespace = true
insert_final_newline = true
[*.s]
[*.{s,inc}]
indent_style = space
indent_size = 2

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# Boot Firmware for CHIBI PC-09
TODO: Description of what the firmware does for the PC-09.
This is the firmware for the CHIBI PC-09. In the future it will provide the
CHIBI with initialization code, a UART driver, some self test features.
## Building the Firmware
You will need GNU `make`, and [`asm6809`](https://www.6809.org.uk/asm6809) to
build the firmware. Obtaining a working copy of `asm6809` could be difficult if
you aren't on Debian, Ubuntu, or Windows as instructions for building it are not
given on the `asm6809` website. Functional instructions for building from Git or
tarball are given here:
Building the firmware from source requires [LWTOOLS](http://www.lwtools.ca/) for
building S-Records of the ROM, and `mot2bin` from
[F9DASM](https://github.com/Arakula/f9dasm) for building binary images. A GNU
Make makefile is provided for building on Linux.
### Using the Makefile
To generate an S-Record run:
```sh
git clone https://www.6809.org.uk/git/asm6809.git
cd asm6809
./configure
make
sudo make install
make boot.s19
```
From there all you should have to do to generate a `boot.bin` is:
To generate a binary run:
```sh
git clone https://github.com/amberisvibin/chibi-pc09.git
cd chibi-pc09
make
```
The makefile also can clean up after itself:
```sh
make clean
```
## Firmware Licensing
This firmware like the rest of the CHIBI PC-09 is licensed under the MIT

5
code/boot/linkscript Normal file
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section RESET load 8000
section SERIAL
section MEMTEST
section VECTORS high 100000

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@@ -8,25 +8,45 @@
# Project Defaults & Folders
# ------------------------------------------------------------------------------
TARGET := boot.bin
SRCDIR := src/
MAINSRC := $(SRCDIR)boot.s
SRCS := $(wildcard $(SRCDIR)*.s)
TARGET := boot
TARGREC := $(TARGET).s19
TARGROM := $(TARGET).bin
SRCDIR := src/
BUILDDIR := build/
SRCS := $(wildcard $(SRCDIR)*.s)
OBJS := $(patsubst $(SRCDIR)%.s,$(BUILDDIR)%.o,$(SRCS))
INCS := $(wildcard $(SRCDIR)*.inc)
# ------------------------------------------------------------------------------
# Toolchain Definitions
# ------------------------------------------------------------------------------
AS := asm6809
AS := lwasm
LD := lwlink
FIX := mot2bin
ASFLAGS := -f obj
LDFLAGS := -f srec -m map.txt -s linkscript
# ------------------------------------------------------------------------------
# Rules and Phony Targets
# ------------------------------------------------------------------------------
all: $(TARGET)
all: $(TARGROM)
$(TARGET): $(SRCS)
$(AS) -o $(TARGET) $(MAINSRC)
# Fix srec into flashable bin file
$(TARGROM): $(TARGREC)
$(FIX) -out $@ $<
# Link objects
$(TARGREC): $(OBJS)
$(LD) $(LDFLAGS) -o $@ $^
# Assemble objects
$(OBJS): $(BUILDDIR)%.o : $(SRCDIR)%.s
-@mkdir -p $(BUILDDIR)
$(AS) $(ASFLAGS) -o $@ $<
clean:
rm -v $(TARGET)
@echo 'Cleaning up intermediary files...'
@rm -rv $(TARGROM) $(TARGREC) map.txt $(BUILDDIR)

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@@ -1,52 +0,0 @@
; CHIBI PC-09 Prototype #1 Boot ROM
; (Copyright (c) 2024 Amber Zeller
; UART registers
UART EQU $7F00
; When DLAB = 0:
BUFR EQU UART ; TX/RX Buffer (Read for RX, Write for TX)
IER EQU UART+1 ; Interrupt Enable Register
IIR EQU UART+1 ; Interrupt Enable Register (Upon Read)
; When DLAB = 1
DLL EQU UART ; Divisor Latch (LSB)
DLM EQU UART+1 ; Divisor Latch (MSB)
FCR EQU UART+2 ; FIFO Control Register (Upon Write)
LCR EQU UART+3 ; Line Control Register
MCR EQU UART+4 ; MODEM Control Register
LSR EQU UART+5 ; Line Status Register
MSR EQU UART+6 ; MODEM Status Register
SCR EQU UART+7 ; Scratch Register (Not for control just spare RAM)
ORG $8000
RESET
; UART Setup
lda %11000001 ; 8n1 serial, enable DLAB
sta LCR
lda $00 ; Set divisor to 12 (9600 baud)
sta DLL
lda $0C
sta DLM
lda %11000000 ; 8n1 serial, disable DLAB
sta LCR
lda %01000000 ; Enable RTS
sta MCR
lda 'H ; send H
sta BUFR
ORG $FFF0
; Reset/Interrupt Vectors
fdb $0000 ; Reserved
fdb $0000 ; SWI3
fdb $0000 ; SWI2
fdb $0000 ; FIRQ
fdb $0000 ; IRQ
fdb $0000 ; SWI
fdb $0000 ; NMI
fdb RESET ; Reset

107
code/boot/src/hardware.inc Normal file
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; CHIBI PC-09 Hardware Definitions
; Copyright (c) 2024-2025 Amber Zeller, Gale Faraday
; Licensed under MIT
; vim: ft=asm
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Hardware Base Addresses
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
SRAM_BASE EQU $0000 ; SRAM Base Address
UART_BASE EQU $7F00 ; UART Base Address
ROM_BASE EQU $8000 ; ROM Base Address and Entry Point
VECS_BASE EQU $FFF0 ; Vectors Base Address
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Stack Base Address and Size Information
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
STACK_BOTTOM EQU $0100 ; Bottom address of system stack
STACK_DEPTH EQU $FF ; System stack's depth
STACK_TOP EQU STACK_BOTTOM+STACK_DEPTH ; Top address of system stack
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; UART Registers and Flags
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; When UARTF_LCR_DLAB = 0:
UART_BUFR EQU UART_BASE ; TX/RX Buffer (Read for RX, Write for TX)
UART_RBR EQU UART_BASE ; RX Buffer Register
UART_THR EQU UART_BASE ; TX Holding Register
UART_IER EQU UART_BASE+1 ; Interrupt Enable Register
; When UARTF_LCR_DLAB = 1:
UART_DLL EQU UART_BASE ; Divisor Latch (LSB)
UART_DLM EQU UART_BASE+1 ; Divisor Latch (MSB)
; Independent of DLAB:
UART_IIR EQU UART_BASE+2 ; Interrupt Ident Register (Upon Read)
UART_FCR EQU UART_BASE+2 ; FIFO Control Register (Upon Write)
UART_LCR EQU UART_BASE+3 ; Line Control Register
UART_MCR EQU UART_BASE+4 ; MODEM Control Register
UART_LSR EQU UART_BASE+5 ; Line Status Register
UART_MSR EQU UART_BASE+6 ; MODEM Status Register
UART_SCR EQU UART_BASE+7 ; Scratch Register (Not for control just spare RAM)
; UART Flags for Interrupt Enable Register:
UARTF_IER_ERBFI EQU %10000000 ; Enable Received Data Available Interrupt
UARTF_IER_ETBEI EQU %01000000 ; Enable Transmitter Holding Register Empty Interrupt
UARTF_IER_ELSI EQU %00100000 ; Enable Receiver Line Status Interrupt
UARTF_IER_EDSSI EQU %00010000 ; Enable MODEM Status Interrupt
; UART Flags for FIFO Control Register:
UARTF_FCR_FE EQU %10000000 ; FIFO Enabled
UARTF_FCR_RFR EQU %01000000 ; RCVR FIFO Reset
UARTF_FCR_XFR EQU %00100000 ; XMIT FIFO Reset
UARTF_FCR_DMS EQU %00010000 ; DMA Mode Select
UARTF_FCR_RTL EQU %00000010 ; RCVR Trigger (LSB)
UARTF_FCR_RTM EQU %00000001 ; RCVR Trigger (MSB)
; UART Flags for Interrupt Ident Register:
UARTF_IIR_INP EQU %10000000 ; Reset if Interrupt Pending; 'INP' = Interrupt Not Pending
UARTF_IIR_IIDM EQU %01110000 ; Interrupt ID Mask
UARTF_IIR_FEM EQU %00000011 ; FIFOs Enabled Mask
; UART Flags for Line Control Register:
UARTF_LCR_WLS EQU %11000000 ; Word Length Select Bits
UARTF_LCR_STB EQU %00100000 ; Stop Bits
UARTF_LCR_PEN EQU %00010000 ; Parity Enable
UARTF_LCR_EPS EQU %00001000 ; Even Parity Select
UARTF_LCR_SPR EQU %00000100 ; Stick Parity
UARTF_LCR_BRK EQU %00000010 ; Set Break
UARTF_LCR_DLAB EQU %00000001 ; Divisor Latch Access Bit
; UART Flags for MODEM Control Register:
UARTF_MCR_DTR EQU %10000000 ; Data Terminal Ready
UARTF_MCR_RTS EQU %01000000 ; Enabling Request to Send
UARTF_MCR_OUT1 EQU %00100000 ; Out 1
UARTF_MCR_OUT2 EQU %00010000 ; Out 2
UARTF_MCR_LOOP EQU %00001000 ; Loop
; UART Flags for Line Status Register:
UARTF_LSR_DR EQU %10000000 ; Data Ready
UARTF_LSR_OE EQU %01000000 ; Overrun Error
UARTF_LSR_PE EQU %00100000 ; Parity Error
UARTF_LSR_FE EQU %00010000 ; Framing Error
UARTF_LSR_BI EQU %00001000 ; Break Interrupt
UARTF_LSR_THRE EQU %00000100 ; Transmitter Holding Register
UARTF_LSR_TEMT EQU %00000010 ; Transmitter Empty
UARTF_LSR_FIFO EQU %00000001 ; Error in RCVR FIFO
; UART Flags for MODEM Status Register:
UARTF_MSR_DCTS EQU %10000000 ; Delta Clear to Send
UARTF_MSR_DDSR EQU %01000000 ; Delta Data Set Ready
UARTF_MSR_TERI EQU %00100000 ; Trailing Edge Ring Indicator
UARTF_MSR_DDCD EQU %00010000 ; Delta Data Carrier Detect
UARTF_MSR_CTS EQU %00001000 ; Clear To Send
UARTF_MSR_DSR EQU %00000100 ; Data Set Ready
UARTF_MSR_RI EQU %00000010 ; Ring Indicator
UARTF_MSR_DCD EQU %00000001 ; Data Carrier Detect

42
code/boot/src/memtest.s Normal file
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; CHIBI PC-09 Prototype #1 Boot ROM -- Memory Testing Routines
; Copyright (c) 2024-2025 Amber Zeller, Gale Faraday
; Licensed under MIT
INCLUDE "hardware.inc"
INCLUDE "serial.inc"
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Memory Testing Routines
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
SECTION MEMTEST
; RAM testing routine. Ported to 6809 from 6800, based on source for ROBIT-2 for
; MIKBUG.
RAMTEST
ldx #SRAM_BASE
AGAIN@ ; Store 1 in memory
lda #1 ; Set [X] to 1
sta 0,x
cmpa 0,x ; If failed print out an error indicator
bne ERR@
NEXT@ ; Loop point for next address
asla ; Shift A and [X] left
asl 0,x
cmpa 0,x ; Compare A and [X]
bne ERR@
cmpa #$80 ; Only test up to $80
bne NEXT@ ; Loop if not $80
cmpx #$60FF ; Compare X to end of RAM
beq PASS@ ; Finish if we're at the end
leax 1,x ; Increment X
bra AGAIN@
ERR@ ; Write out error indicator
ldb #'X
jsr OUTCHAR
PASS@ ; Pass test
ldb #'P
jsr OUTCHAR
rts

7
code/boot/src/reset.inc Normal file
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; CHIBI PC-09 Prototype #1 -- Reset Handler Header
; Copyright (c) 2025 Amber Zeller, Gale Faraday
; Licensed under MIT
; vim: ft=asm
RESET IMPORT

49
code/boot/src/reset.s Normal file
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; CHIBI PC-09 Prototype #1 Boot ROM -- Reset Handler
; Copyright (c) 2024-2025 Amber Zeller, Gale Faraday
; Licensed under MIT
INCLUDE "hardware.inc"
INCLUDE "serial.inc"
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Hardware Initialization Routines
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
SECTION RESET
EXPORT RESET
RESET
CLRSTACK
; Initialize the system stack
lda #$00 ; Initialize A & X to zero out the stack
ldx #$0000
NEXT@
sta STACK_BOTTOM,x ; Write a zero and progress to the next byte
leax 1,x
cmpx #STACK_DEPTH ; See if we're at the top of the stack yet
blo NEXT@ ; Loop if we aren't at the end yet
lds STACK_TOP ; Set S to top of newly cleared stack
SERINIT
; 8n1 Serial Enable DLAB
lda #UARTF_LCR_WLS|UARTF_LCR_DLAB
sta UART_LCR
; REVIEW: Potential endianness hiccough here
ldd #$0C00 ; Set divisor to 12 (9600 baud)
sta UART_DLM
stb UART_DLL
lda #(UARTF_LCR_WLS) ; 8n1 serial, disable DLAB
sta UART_LCR
lda #(UARTF_MCR_RTS) ; Enable Request-to-Send
sta UART_MCR
lda #'H ; send 'H'
sta UART_BUFR
WAIT
sync ; Wait for interrupts
nop
bra WAIT

8
code/boot/src/serial.inc Normal file
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; CHIBI PC-09 Prototype #1 -- Serial Driver Header
; Copyright (c) 2025 Amber Zeller, Gale Faraday
; Licensed under MIT
; vim: ft=asm
OUTCHAR IMPORT
OUTSTR IMPORT

45
code/boot/src/serial.s Normal file
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; CHIBI PC-09 Prototype #1 Boot ROM -- Serial Driver
; Copyright (c) 2024-2025 Amber Zeller, Gale Faraday
; Licensed under MIT
INCLUDE "hardware.inc"
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Serial UART Driver
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
SECTION SERIAL
EXPORT OUTCHAR
EXPORT OUTSTR
; Writes a char to the UART in non FIFO mode, preserves A.
; @param b: char to write
OUTCHAR
pshs a ; Preserve A
NOTREADY@
lda UART_LSR ; if LSR.THRE == 1 then write
anda UARTF_LSR_THRE
bne NOTREADY@ ; Loop if UART not ready yet
stb UART_BUFR ; Write char
puls a ; Restore A
rts
; Writes a null terminated string to the UART in non FIFO mode, clobbers A and
; B.
; @param x: null terminated string start address.
OUTSTR
ldb 0,x ; Get the next value from X
cmpb #$00 ; Make sure that we aren't at a terminator
beq END@
leax 1,x ; Increment X for our next char
NOTREADY@ ; Loop point for UART waiting
lda UART_LSR ; Wait for UART to be ready
anda UARTF_LSR_THRE
bne NOTREADY@
stb UART_BUFR ; Actually do our write
bra OUTSTR ; Reset for the next char
END@ ; Jump point for end of routine
rts

23
code/boot/src/vecs.s Normal file
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; CHIBI PC-09 Prototype #1 Boot ROM -- Interrupt and Reset Vectors
; Copyright (c) 2024-2025 Amber Zeller, Gale Faraday
; Licensed under MIT
INCLUDE "reset.inc"
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Interrupt and Reset Vectors
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
SECTION VECTORS
VECTORS
fdb $0000 ; Reserved
fdb $0000 ; SWI3
fdb $0000 ; SWI2
fdb $0000 ; FIRQ
fdb $0000 ; IRQ
fdb $0000 ; SWI
fdb $0000 ; NMI
fdb RESET ; Reset

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# Motorola 6809 and TI SN74LS612 Timing
## Motorola 6809 Timing
Dual phase clock, E and Q. Staggered by half a clock.
1, 1.5, or 2 mHz. Nanosecond timing will be listed for all 3 speeds.
* On Q rise, address and R/-W output is valid.
* On E rise, data output is valid.
* Time between Q rise and E rise is (approx) minimum 200/130/80ns and max 250/166/125ns.
* Time between address and R/-W output to data output.
* On E fall, data input is read. Address and R/-W output become invalid.
* Data input must be valid for minimum 80/60/40ns before E fall.
* Output data on Q fall to ensure data input is valid.
## TI SN74LS612 Timing
Async
### Write mode:
* -Strobe occurs to perform write.
* -Strobe pulse must be at least 75ns.
* Data must be valid 75ns before -strobe fall.
* -CS, R/-W, RS must be low at least 20ns before -strobe fall.
* -CS, R/-W, RS, Data must be valid at least 20ns after -strobe rise.
## Interface
### 6809 Write to SN74LS612
## Sources
* Motorola MC6809 Datasheet, undated
* Motorola MC6809E Datasheet, 1984
* TI SN54LS610, SN54LS612, SN74LS610 THRU SN74LS613 Datasheet, 1981-1988

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@@ -1,6 +0,0 @@
TTL devices can handle CMOS input. HD6309 -> 74LS612
CMOS devices may or may not handle TTL input. 74LS612 -> peripherals
62256 SRAM, 28C256 EEPROM, 16550 UART all handle TTL input.
82C42 lists it's outputs as TTL compatible, but says nothing for inputs.
Must ensure all peripherals are rated for TTL input.

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@@ -3,7 +3,6 @@
File descriptions:
- links.txt contains useful links i would like to keep
- 6809-sn74ls612_timing.md contains notes on the mmu and cpu interface
- tech-spec.md contains basic info on layout of system (outdated)
- timing.html contains info on vga timing pulled from https://martin.hinner.info/vga/timing.html
- vga_ram.txt contains notes on ram size for the vga card

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@@ -1,14 +0,0 @@
RAM:
https://www.jameco.com/z/HM62256LP-70-Major-Brands-IC-62256LP-70-Low-Power-CMOS-SRAM-256K-Bit-32Kx8-70ns_82472.html
UART:
https://www.jameco.com/z/PC16550DN-Major-Brands-Universal-Asynchronous-Receiver-Transmitter-with-FIFOs-DIP-40_27596.html
Not available on Jameco: HD63C09, 28C256, uPD72020, VT82C42, 74LS612.
eBay may be a better choice.
12Mhz Passive Crystal 20pf:
https://www.jameco.com/z/TQR49S12M0000A2040-Jameco-ValuePro-12-000MHz-HC49-Us-20pF-Crystal_325198.html
1.8432 MHz Full Can Crystal Oscillator:
https://www.jameco.com/z/MX045-3C-1M843200-JVP-Jameco-ValuePro-1-8432-MHz-Full-Can-Crystal-Oscillator_27879.html

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# Font
An 8x8 font. Also a 16x16 temp logo.

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