Merge branch 'memtest' of https://gitea.ambersplace.net/gfaraday/chibi-pc09 into memtest

Reviewed-on: #1

.gitignore

@@ -1,3 +1,3 @@
 widgets.qss
 *.lck
-
+prototype-1-backups/

README.md

@@ -1,17 +1,19 @@
 # chibi pc-09
-![GitHub last commit](https://img.shields.io/github/last-commit/amberisvibin/chibi-pc80)
+
+![Gitea last commit](https://img.shields.io/gitea/last-commit/amberisvibin/chibi-pc09?gitea_url=https%3A%2F%2Fgitea.ambersplace.net&style=for-the-badge&label=Last%20Gitea%20Commit)
+![GitHub last commit](https://img.shields.io/github/last-commit/amberisvibin/chibi-pc09?style=for-the-badge&label=Last%20Github%20Commit)
 
 ## Description
 
-The PC-09 will be a 6309 based microcomputer with a 74LS612 MMU, uPD72020 graphics, PS/2 keyboard and mouse input, and a capable UART. 
+The PC-09 will be a 6309 based microcomputer with an MMU using 74HC670 register files and dual 16550 UARTs. The plan is to eventually add uPD7220 graphics and PS/2 mouse and keyboard.
 
-The MMU will allow up to 2 megabytes of I/O to be paged into the address space. Pages are 4k. System storage will be paged into the address space as well, as it will be either EEPROM or flash. 
+The two 74HC670s will take the top 4 bits of the address bus and expand them to 8 bits, turning the 16 bit cpu address space into a 20 bit address space capable of addressing 1MB of memory. Memory pages are 4KB. Being a register file, any page can be mapped to any slot, allowing complex memory management schemes.
 
-The uPD72020 is a very advanced graphics chip for it's time, capable of accelerated drawing of lines, shapes, fills, and characters. It can be coerced into outputting a VGA signal at 640x480 and *maybe* 800x600. 
+The 16550 UART is capable of interrupt driven operation with FIFOs, allowing for characters to be processed in batches rather than individually, minimizing task switch delays. They also support hardware flow control, and some versions can automatically assert RTS when the FIFO is nearing full.
 
-Keyboard and mouse will be handled by the VIA VT82C42. It is an Intel 8242 compatible controller capable of both PS/2 keyboard and mouse. It's interface is relatively simple, which makes connection easy. It relies on interrupts, so an interrupt system will be required.
+The uPD7220 graphics are very powerful, allowing 16 colors at 640x480, but it is a complex chip to get working. It will be left for a later date.
 
-To avoid the infamous 65C22 bug, the system will use the 16550 UART from the PC ecosystem. It is *relatively* easy to interface this to a 6800 style bus. It has more features than a 65C22 as well. As configured, it will be stable up to 38,400 baud. 
+The solution for PS/2 keyboard and mouse have not yet been decided.
 
 ## Progress
 
@@ -19,6 +21,10 @@ I had started wiring together a board for prototyping, but it was destroyed in h
 
 Prototype 1 is currently in progress. It will be a much simpler system. It will have no MMU, just the CPU, some RAM, some ROM, and the UART.
 
+The PCB and parts for Prototype #1 have been ordered, and assembly will begin soon. Initial test code is now available in the code/ directory.
+
+Assembly is in progress.
+
 ## License
 
-This project is licensed under the MIT license. This applies to both the hardware (schematics, bill of materials, pcb layouts) and documentation. This does *not* apply to the datasheets/ directory, the books/ directory or code/assist09/assist09.asm. Those files belong to their respective copyright holders.
+This project is licensed under the MIT license. This applies to both the hardware (schematics, bill of materials, pcb layouts) and documentation. This does *not* apply to the datasheets/ directory, the books/ directory or code/assist09/. Those files belong to their respective copyright holders.

code/README.md

@@ -1,13 +1,7 @@
 # Code
 
-## assist09/
+These are the sources for the boot code for Prototype #1. ASSIST09 will eventually be integrated.
 
-assist09.asm is the original motorola version, and relies on the as9 assembler found [here](http://home.hccnet.nl/a.w.m.van.der.horst/m6809.html).
+The version of ASSIST09 that is being used has been modified for asm6809 by the [MECB](https://github.com/DigicoolThings/MECB) project and is available [here](https://github.com/DigicoolThings/MECB/blob/main/MECB_6809_CPU/ASSIST09/src/ASSIST09_Original_ASM6809.asm).
 
-assemble.sh will assemble assist09.asm to an s19 file and use gnu binutils objcopy to turn that into a bin file.
+Information for building the boot code is under boot/README.md.
-
-## boot/
-
-the boot code for prototype 1, uses the lwtools assembler.
-
-assemble.sh will assemble boot.s to an s19 file and use gnu binutils objcopy to turn that into a bin file.

code/assist09/ASSIST09_Original_ASM6809.asm

@@ -68,33 +68,33 @@ NUMFUN  EQU     11              ; NUMBER OF AVAILABLE FUNCTIONS
 * THEY ARE EQUIVALENT TO OFFSETS IN THE TABLE.
 * RELATIVE POSITIONING MUST BE MAINTAINED
 
-.AVTBL  EQU     0               ; ADDRESS OF VECTOR TABLE
+_AVTBL  EQU     0               ; ADDRESS OF VECTOR TABLE
-.CMDL1  EQU     2               ; FIRST COMMAND LIST
+_CMDL1  EQU     2               ; FIRST COMMAND LIST
-.RSVD   EQU     4               ; RESERVED HARDWARE VECTOR
+_RSVD   EQU     4               ; RESERVED HARDWARE VECTOR
-.SWI3   EQU     6               ; SWI3 ROUTINE
+_SWI3   EQU     6               ; SWI3 ROUTINE
-.SWI2   EQU     8               ; SWI2 ROUTINE
+_SWI2   EQU     8               ; SWI2 ROUTINE
-.FIRQ   EQU     10              ; FIRQ ROUTINE
+_FIRQ   EQU     10              ; FIRQ ROUTINE
-.IRQ    EQU     12              ; IRQ ROUTINE
+_IRQ    EQU     12              ; IRQ ROUTINE
-.SWI    EQU     14              ; SWI ROUTINE
+_SWI    EQU     14              ; SWI ROUTINE
-.NMI    EQU     16              ; NMI ROUTINE
+_NMI    EQU     16              ; NMI ROUTINE
-.RESET  EQU     18              ; RESET ROUTINE
+_RESET  EQU     18              ; RESET ROUTINE
-.CION   EQU     20              ; CONSOLE ON
+_CION   EQU     20              ; CONSOLE ON
-.CIDTA  EQU     22              ; CONSOLE INPUT DATA
+_CIDTA  EQU     22              ; CONSOLE INPUT DATA
-.CIOFF  EQU     24              ; CONSOLE INPUT OFF
+_CIOFF  EQU     24              ; CONSOLE INPUT OFF
-.COON   EQU     26              ; CONSOLE OUTPUT ON
+_COON   EQU     26              ; CONSOLE OUTPUT ON
-.CODTA  EQU     28              ; CONSOLE OUTPUT DATA
+_CODTA  EQU     28              ; CONSOLE OUTPUT DATA
-.COOFF  EQU     30              ; CONSOLE OUTPUT OFF
+_COOFF  EQU     30              ; CONSOLE OUTPUT OFF
-.HSDTA  EQU     32              ; HIGH SPEED PRINTDATA
+_HSDTA  EQU     32              ; HIGH SPEED PRINTDATA
-.BSON   EQU     34              ; PUNCH/LOAD ON
+_BSON   EQU     34              ; PUNCH/LOAD ON
-.BSDTA  EQU     36              ; PUNCH/LOAD DATA
+_BSDTA  EQU     36              ; PUNCH/LOAD DATA
-.BSOFF  EQU     38              ; PUNCH/LOAD OFF
+_BSOFF  EQU     38              ; PUNCH/LOAD OFF
-.PAUSE  EQU     40              ; TASK PAUSE ROUTINE
+_PAUSE  EQU     40              ; TASK PAUSE ROUTINE
-.EXPAN  EQU     42              ; EXPRESSION ANALYZER
+_EXPAN  EQU     42              ; EXPRESSION ANALYZER
-.CMDL2  EQU     44              ; SECOND COMMAND LIST
+_CMDL2  EQU     44              ; SECOND COMMAND LIST
-.ACIA   EQU     46              ; ACIA ADDRESS
+_ACIA   EQU     46              ; ACIA ADDRESS
-.PAD    EQU     48              ; CHARACTER PAD AND NEW LINE PAD
+_PAD    EQU     48              ; CHARACTER PAD AND NEW LINE PAD
-.ECHO   EQU     50              ; ECHO/LOAD AND NULL BKPT FLAG
+_ECHO   EQU     50              ; ECHO/LOAD AND NULL BKPT FLAG
-.PTM    EQU     52              ; PTM ADDRESS
+_PTM    EQU     52              ; PTM ADDRESS
 NUMVTR  EQU     52/2+1          ; NUMBER OF VECTORS
 HIVTR   EQU     52              ; HIGHEST VECTOR OFFSET
 
@@ -108,7 +108,7 @@ HIVTR   EQU     52              ; HIGHEST VECTOR OFFSET
 * DEFINED HEREIN.
 ******************************************
 WORKPG  EQU     ROMBEG+RAMOFS   ; SETUP DIRECT PAGE ADDRESS
-*       SETDP   =WORKPG         ; NOTIFY ASSEMBLER
+        SETDP   WORKPG!>8       ; NOTIFY ASSEMBLER
         ORG     WORKPG+256      ; READY PAGE DEFINITIONS
 
 * THE FOLLOWING THRU BKPTOP MUST RESIDE IN THIS ORDER
@@ -341,12 +341,12 @@ SIGNON  FCC     /ASSIST09/      ; SIGNON EYE-CATCHER
 ZMONTR  STS     <RSTACK         ; SAVE FOR BAD STACK RECOVERY
         TST     1,S             ; ? INIT CONSOLE AND SEND MSG
         BNE     ZMONT2          ; BRANCH IF NOT
-        JSR     [VECTAB+.CION,PCR] ; READY CONSOLE INPUT
+        JSR     [VECTAB+_CION,PCR] ; READY CONSOLE INPUT
-        JSR     [VECTAB+.COON,PCR] ; READY CONSOLE OUTPUT
+        JSR     [VECTAB+_COON,PCR] ; READY CONSOLE OUTPUT
         LEAX    SIGNON,PCR         ; READY SIGNON EYE-CATCHER
         SWI                     ; PERFORM
         FCB     PDATA           ; PRINT STRING
-ZMONT2  LDX     <VECTAB+.PTM    ; LOAD PTM ADDRESS
+ZMONT2  LDX     <VECTAB+_PTM    ; LOAD PTM ADDRESS
         BEQ     CMD             ; BRANCH IF NOT TO USE A PTM
         CLR     PTMTM1-PTM,X    ; SET LATCH TO CLEAR RESET
         CLR     PTMTM1+1-PTM,X  ; AND SET GATE HIGH
@@ -423,10 +423,10 @@ CMD3    LBSR   READ             ; OBTAIN NEXT CHARACTER
 * GOT COMMAND, NOW SEARCH TABLES
 CMDGOT  SUBA   #CR              ; SET ZERO IF CARRIAGE RETURN
         STA    -3,U             ; SETUP FLAG
-        LDX    <VECTAB+.CMDL1   ; START WITH FIRST CMD LIST
+        LDX    <VECTAB+_CMDL1   ; START WITH FIRST CMD LIST
 CMDSCH  LDB    ,X+              ; LOAD ENTRY LENGTH
         BPL    CMDSME           ; BRANCH IF NOT LIST END
-        LDX    <VECTAB+.CMDL2   ; NOW TO SECOND CMD LITS
+        LDX    <VECTAB+_CMDL2   ; NOW TO SECOND CMD LITS
         INCB                    ; ? TO CONTINUE TO DEFAULT LIST
         BEQ     CMDSCH          ; BRANCH IF SO
 CMDBAD  LDS     <PSTACK         ; RESTORE STACK
@@ -562,7 +562,7 @@ ZOUTHX  ADDA    #$90            ; PREPARE A-F ADJUST
         DAA                     ; ADJUST
         ADCA    #$40            ; PREPARE CHARACTER BITS
         DAA                     ; ADJUST
-SEND    JMP     [VECTAB+.CODTA,PCR] ; SEND TO OUT HANDLER
+SEND    JMP     [VECTAB+_CODTA,PCR] ; SEND TO OUT HANDLER
 
 ZOT4HS  BSR     ZOUT2H          ; CONVERT FIRST BYTE
 ZOT2HS  BSR     ZOUT2H          ; CONVERT BYTE TO HEX
@@ -588,7 +588,7 @@ ZSPACE  LDA     #'              ; LOAD BLANK
 ZVSWTH  LDA     1,S             ; LOAD REQUESTERS A
         CMPA    #HIVTR          ; ? SUB-CODE TOO HIGH
         BHI     ZOTCH3          ; IGNORE CALL IF SO
-        LDY     <VECTAB+.AVTBL  ; LOAD VECTOR TABLE ADDRESS
+        LDY     <VECTAB+_AVTBL  ; LOAD VECTOR TABLE ADDRESS
         LDU     A,Y             ; U=OLD ENTRY
         STU     4,S             ; RETURN OLD VALUE TO CALLERS X
         STX     -2,S            ; ? X=0
@@ -619,7 +619,7 @@ ZINCH   BSR     XQCIDT          ; CALL INPUT DATA APPENDAGE
         BNE     ZIN2            ; NO, TEST ECHO BYTE
         LDA     #LF             ; LOAD LINE FEED
         BSR     SEND            ; ALWAYS ECHO LINE FEED
-ZIN2    TST     <VECTAB+.ECHO   ; ? ECHO DESIRED
+ZIN2    TST     <VECTAB+_ECHO   ; ? ECHO DESIRED
         BNE     ZOTCH3          ; NO, RETURN
 * FALL THROUGH TO OUTCH
 ************************************************
@@ -718,8 +718,8 @@ CHKWT   BSR     XQPAUS          ; PAUSE FOR A MOMENT
         RTS                     ; AND RETURN
 
 * SAVE MEMORY WITH JUMPS
-XQPAUS  JMP   [VECTAB+.PAUSE,PCR] ; TO PAUSE ROUTINE
+XQPAUS  JMP   [VECTAB+_PAUSE,PCR] ; TO PAUSE ROUTINE
-XQCIDT  JSR   [VECTAB+.CIDTA,PCR] ; TO INPUT ROUTINE
+XQCIDT  JSR   [VECTAB+_CIDTA,PCR] ; TO INPUT ROUTINE
         ANDA  #$7F              ; STRIP PARITY
         RTS                     ; RETURN TO CALLER
 
@@ -821,7 +821,7 @@ FIRQR   EQU     RTI             ; IMMEDIATE RETURN
 * OUTPUT: C=0 IF NO DATA READY, C=1 A=CHARACTER
 * U VOLATILE
 
-CIDTA   LDU     <VECTAB+.ACIA   ; LOAD ACIA ADDRESS
+CIDTA   LDU     <VECTAB+_ACIA   ; LOAD ACIA ADDRESS
         LDA     ,U              ; LOAD STATUS REGISTER
         LSRA                    ; TEST RECEIVER REGISTER FLAG
         BCC     CIRTN           ; RETURN IF NOTHING
@@ -833,7 +833,7 @@ CIRTN   RTS                     ; RETURN TO CALLER
 * A,X VOLATILE
 CION   EQU      *
 COON   LDA      #3              ; RESET ACIA CODE
-       LDX      <VECTAB+.ACIA   ; LOAD ACIA ADDRESS
+       LDX      <VECTAB+_ACIA   ; LOAD ACIA ADDRESS
        STA      ,X              ; STORE INTO STATUS REGISTER
        LDA      #$51            ; SET CONTROL
        STA      ,X              ; REGISTER UP
@@ -849,14 +849,14 @@ COOFF EQU       RTS             ; CONSOLE OUTPUT OFF
 * ALL REGISTERS TRANSPARENT
 
 CODTA   PSHS    U,D,CC          ; SAVE REGISTERS,WORK BYTE
-        LDU     <VECTAB+.ACIA   ; ADDRESS ACIA
+        LDU     <VECTAB+_ACIA   ; ADDRESS ACIA
         BSR     CODTAO          ; CALL OUTPUT CHAR SUBROUTINE
         CMPA    #DLE            ; ? DATA LINE ESCAPE
         BEQ     CODTRT          ; YES, RETURN
-        LDB     <VECTAB+.PAD    ; DEFAULT TO CHAR PAD COUNT
+        LDB     <VECTAB+_PAD    ; DEFAULT TO CHAR PAD COUNT
         CMPA    #CR             ; ? CR
         BNE     CODTPD          ; BRANCH NO
-        LDB     <VECTAB+.PAD+1  ; LOAD NEW LINE PAD COUNT
+        LDB     <VECTAB+_PAD+1  ; LOAD NEW LINE PAD COUNT
 CODTPD  CLRA                    ; CREATE NULL
         STB     ,S              ; SAVE COUNT
         FCB     SKIP2           ; ENTER LOOP
@@ -866,10 +866,10 @@ CODTLP  BSR     CODTAO          ; SEND NULL
 CODTRT  PULS    PC,U,D,CC       ; RESTORE REGISTERS AND RETURN
 
 CODTAD  LBSR    XQPAUS          ; TEMPORARY GIVE UP CONTROL
-CODTAO  LDB     1,U             ; LOAD ACIA CONTROL REGISTER
+CODTAO  LDB     ,U              ; LOAD ACIA CONTROL REGISTER
-        BITB    #$02            ; ? TX REGISTER CLEAR >LSAB FIXME
+        BITB    #$02            ; ? TX REGISTER CLEAR
-        BNE     CODTAD          ; RELEASE CONTROL IF NOT
+        BEQ     CODTAD          ; RELEASE CONTROL IF NOT
-        STA     ,U              ; STORE INTO DATA REGISTER
+        STA     1,U             ; STORE INTO DATA REGISTER
         RTS                     ; RETURN TO CALLER
 *E
 
@@ -975,15 +975,15 @@ BYTHEX  SWI                    ; GET NEXT HEX
 *                  S+1=FRAME COUNT/CHECKSUM
 *                  S+0=BYTE COUNT
 
-BSDPUN  LDU     <VECTAB+.PAD    ; LOAD PADDING VALUES
+BSDPUN  LDU     <VECTAB+_PAD    ; LOAD PADDING VALUES
         LDX     4,S             ; X=FROM ADDRESS
         PSHS    U,X,D           ; CREATE STACK WORK AREA
         LDD     #24             ; SET A=0, B=24
-        STB     <VECTAB+.PAD    ; SETUP 24 CHARACTER PADS
+        STB     <VECTAB+_PAD    ; SETUP 24 CHARACTER PADS
         SWI                     ; SEND NULLS OUT
         FCB     OUTCH           ; FUNCTION
         LDB     #4              ; SETUP NEW LINE PAD TO 4
-        STD     <VECTAB+.PAD    ; SETUP PUNCH PADDING
+        STD     <VECTAB+_PAD    ; SETUP PUNCH PADDING
 * CALCULATE SIZE
 BSPGO   LDD     8,S             ; LOAD TO
         SUBD    2,S             ; MINUS FROM=LENGTH
@@ -1024,14 +1024,14 @@ BSPMRE BSR      BSPUN2          ; SEND OUT NEXT BYTE
        SWI                      ; SEND OUT STRING
        FCB      PDATA           ; FUNCTION
        LDD      4,S             ; RECOVER PAD COUNTS
-       STD      <VECTAB+.PAD    ; RESTORE
+       STD      <VECTAB+_PAD    ; RESTORE
        CLRA                     ; SET Z=1 FOR OK RETURN
        PULS     PC,U,X,D        ; RETURN WITH OK CODE
 BSPUN2 ADDB     ,X              ; ADD TO CHECKSUM
 BSPUNC LBRA     ZOUT2H          ; SEND OUT AS HEX AND RETURN
 
-BSPSTR FCB      'S,'1,EOT       ; CR,LF,NULLS,S,1
+BSPSTR FCB      'S,'1,EOT        ; CR,LF,NULLS,S,1
-BSPEOF FCC      /S9030000FC/    ; EOF STRING
+BSPEOF FCC      /S9030000FC/         ; EOF STRING
        FCB      CR,LF,EOT
 
 * HSDTA - HIGH SPEED PRINT MEMORY
@@ -1084,7 +1084,7 @@ HSHCOK  SWI                     ; SEND CHARACTER
         FCB     OUTCH           ; FUNCTION
         DECB                    ; ? DONE
         BNE     HSHCHR          ; BRANCH NO
-        CPX     2,S             ; ? PAST LAST ADDRESS
+        CMPX    2,S             ; ? PAST LAST ADDRESS
         BHS     HSDRTN          ; QUIT IF SO
         STX     4,S             ; UPDATE FROM ADDRESS
         LDA     5,S             ; LOAD LOW BYTE ADDRESS
@@ -1224,7 +1224,7 @@ BLDNNB  CLRA                    ; NO DYNAMIC DELIMITER
 * BUILD WITH LEADING BLANKS
 BLDNUM  LDA     #'              ; ALLOW LEADING BLANKS
         STA     <DELIM          ; STORE AS DELIMITER
-        JMP     [VECTAB+.EXPAN,PCR]   ; TO EXP ANALYZER
+        JMP     [VECTAB+_EXPAN,PCR]   ; TO EXP ANALYZER
 * THIS IS THE DEFAULT SINGLE ROM ANALYZER. WE ACCEPT:
 * 1) HEX INPUT
 * 2) 'M' FOR LAST MEMORY EXAMINE ADDRESS
@@ -1491,7 +1491,7 @@ CDISPS  PSHS    Y,X             ; SETUP PARAMETERS FOR HSDATA
         CMPD    2,S             ; ? WAS IT COUNT
         BLS     CDCNT           ; BRANCH YES
         STD     ,S              ; STORE HIGH ADDRESS
-CDCNT   JSR     [VECTAB+.HSDTA,PCR] ; CALL PRINT ROUTINE
+CDCNT   JSR     [VECTAB+_HSDTA,PCR] ; CALL PRINT ROUTINE
         PULS    PC,U,Y          ; CLEAN STACK AND END COMMAND
 
 * OBTAIN NUMBER - ABORT IF NONE
@@ -1513,10 +1513,10 @@ CPUNCH  BSR     CDNUM           ; OBTAIN START ADDRESS
         BSR     CDNUM           ; OBTAIN END ADDRESS
         CLR     ,-S             ; SETUP PUNCH FUNCTION CODE
         PSHS    Y,D             ; STORE VALUES ON STACK
-CCALBS  JSR     [VECTAB+.BSON,PCR] ; INITIALIZE HANDLER
+CCALBS  JSR     [VECTAB+_BSON,PCR] ; INITIALIZE HANDLER
-        JSR     [VECTAB+.BSDTA,PCR] ; PERFORM FUNCTION
+        JSR     [VECTAB+_BSDTA,PCR] ; PERFORM FUNCTION
         PSHS    CC              ; SAVE RETURN CODE
-        JSR     [VECTAB+.BSOFF,PCR] ; TURN OFF HANDLER
+        JSR     [VECTAB+_BSOFF,PCR] ; TURN OFF HANDLER
         PULS    CC              ; OBTAIN CONDITION CODE SAVED
         BNE     CDBADN          ; BRANCH IF ERROR
         PULS    PC,Y,X,A        ; RETURN FROM COMMAND
@@ -1546,14 +1546,14 @@ CTRACE  BSR     CDNUM           ; OBTAIN TRACE COUNT
 CDOT    LEAS    2,S             ; RID COMMAND RETURN FROM STACK
 CTRCE3  LDU     [10,S]          ; LOAD OPCODE TO EXECUTE
         STU     <LASTOP         ; STORE FOR TRACE INTERRUPT
-        LDU     <VECTAB+.PTM    ; LOAD PTM ADDRESS
+        LDU     <VECTAB+_PTM    ; LOAD PTM ADDRESS
         LDD     #$0701          ; 7,1 CYCLES DOWN+CYCLES UP
         STD     PTMTM1-PTM,U    ; START NMI TIMEOUT
         RTI                     ; RETURN FOR ONE INSTRUCTION
 
 *************NULLS  -  SET NEW LINE AND CHAR PADDING
 CNULLS  BSR     CDNUM           ; OBTAIN NEW LINE PAD
-        STD     <VECTAB+.PAD    ; RESET VALUES
+        STD     <VECTAB+_PAD    ; RESET VALUES
         RTS                     ; END COMMAND
 
 ******************STLEVEL - SET STACK TRACE LEVEL
@@ -1713,13 +1713,13 @@ CONV2
 ****************************************************
 *            DEFAULT INTERRUPT TRANSFERS           *
 ****************************************************
-RSRVD   JMP     [VECTAB+.RSVD,PCR]      ; RESERVED VECTOR
+RSRVD   JMP     [VECTAB+_RSVD,PCR]      ; RESERVED VECTOR
-SWI3    JMP     [VECTAB+.SWI3,PCR]      ; SWI3 VECTOR
+SWI3    JMP     [VECTAB+_SWI3,PCR]      ; SWI3 VECTOR
-SWI2    JMP     [VECTAB+.SWI2,PCR]      ; SWI2 VECTOR
+SWI2    JMP     [VECTAB+_SWI2,PCR]      ; SWI2 VECTOR
-FIRQ    JMP     [VECTAB+.FIRQ,PCR]      ; FIRQ VECTOR
+FIRQ    JMP     [VECTAB+_FIRQ,PCR]      ; FIRQ VECTOR
-IRQ     JMP     [VECTAB+.IRQ,PCR]       ; IRQ VECTOR
+IRQ     JMP     [VECTAB+_IRQ,PCR]       ; IRQ VECTOR
-SWI     JMP     [VECTAB+.SWI,PCR]       ; SWI VECTOR
+SWI     JMP     [VECTAB+_SWI,PCR]       ; SWI VECTOR
-NMI     JMP     [VECTAB+.NMI,PCR]       ; NMI VECTOR
+NMI     JMP     [VECTAB+_NMI,PCR]       ; NMI VECTOR
 
 ******************************************************
 *            ASSIST09 HARDWARE VECTOR TABLE

code/assist09/assemble-assist09.sh

@@ -1,2 +0,0 @@
-as9 assist09.asm -l s19
-objcopy --input-target=srec --output-target=binary assist09.s19 assist09.bin

code/boot/.editorconfig

@@ -8,7 +8,7 @@ charset = utf-8
 trim_trailing_whitespace = true
 insert_final_newline = true
 
-[*.s]
+[*.{s,inc}]
 indent_style = space
 indent_size = 2
 

code/boot/makefile

@@ -12,6 +12,7 @@ TARGET  := boot.bin
 SRCDIR  := src/
 MAINSRC := $(SRCDIR)boot.s
 SRCS    := $(wildcard $(SRCDIR)*.s)
+INCS    := $(wildcard $(SRCDIR)*.inc)
 
 # ------------------------------------------------------------------------------
 # Toolchain Definitions
@@ -25,7 +26,7 @@ AS := asm6809
 
 all: $(TARGET)
 
-$(TARGET): $(SRCS)
+$(TARGET): $(SRCS) $(INCS)
 	$(AS) -o $(TARGET) $(MAINSRC)
 
 clean:

code/boot/src/boot.s

@@ -1,47 +1,113 @@
-; CHIBI PC-09 Prototype #1 Boot ROM
+; CHIBI PC-09 Prototype #1 Boot ROM -- Hardware Initialization and Reset Vecs
-; (Copyright (c) 2024 Amber Zeller
+; Copyright (c) 2024 Amber Zeller, Gale Faraday
+; Licensed under MIT
 
-; UART registers
+  INCLUDE "src/hardware.inc"
-UART EQU $7F00
 
-; When DLAB = 0:
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-BUFR EQU UART  ; TX/RX Buffer (Read for RX, Write for TX)
+;;
-IER EQU UART+1 ; Interrupt Enable Register
+;; Hardware Initialization Routines
-IIR EQU UART+1 ; Interrupt Enable Register (Upon Read)
+;;
-; When DLAB = 1
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-DLL EQU UART   ; Divisor Latch (LSB)
-DLM EQU UART+1 ; Divisor Latch (MSB)
 
-FCR EQU UART+2 ; FIFO Control Register (Upon Write)
+  SECTION "Reset"
-LCR EQU UART+3 ; Line Control Register
+  ORG ROM_BASE
-MCR EQU UART+4 ; MODEM Control Register
-LSR EQU UART+5 ; Line Status Register
-MSR EQU UART+6 ; MODEM Status Register
-SCR EQU UART+7 ; Scratch Register (Not for control just spare RAM)
-
-  ORG $8000
 
 RESET
-  ; UART Setup
+  ; 8n1 Serial Enable DLAB
-  lda %11000001 ; 8n1 serial, enable DLAB
+  lda #(UARTF_LCR_WLS | UARTF_LCR_DLAB)
-  sta LCR
+  sta UART_LCR
 
-  lda $00       ; Set divisor to 12 (9600 baud)
+  ; REVIEW: Potential endianness hiccough here
-  sta DLL
+  ldd #$0C00           ; Set divisor to 12 (9600 baud)
-  lda $0C
+  sta UART_DLM
-  sta DLM
+  stb UART_DLL
 
-  lda %11000000 ; 8n1 serial, disable DLAB
+  lda #(UARTF_LCR_WLS) ; 8n1 serial, disable DLAB
-  sta LCR
+  sta UART_LCR
 
-  lda %01000000 ; Enable RTS
+  lda #(UARTF_MCR_RTS) ; Enable Request-to-Send
-  sta MCR
+  sta UART_MCR
 
-  lda 'H        ; send H
+  lda 'H               ; send 'H'
-  sta BUFR
+  sta UART_BUFR
 
-  ORG $FFF0
+WAIT
-  ; Reset/Interrupt Vectors
+  sync                 ; Wait for interrupts
+  nop
+  bra WAIT
+
+  SECTION "Serial"
+
+; Writes a char to the UART in non FIFO mode, preserves A.
+; @param b: char to write
+OUTCHAR
+  pshs a               ; Preserve A
+1
+  lda UART_LSR         ; if LSR.THRE == 1 then write
+  anda UARTF_LSR_THRE
+  bne 1B               ; Loop if UART not ready yet
+  stb UART_BUFR        ; Write char
+  puls a               ; Restore A
+  rts
+
+; Writes a null terminated string to the UART in non FIFO mode, clobbers A and
+; B.
+; @param x: null terminated string start address.
+OUTSTR
+  ldb x                ; Get the next value from X
+  cmpb #$00            ; Make sure that mother is non-null
+  beq 2F
+  leax 1,x             ; Increment X for our next char
+1                      ; Loop point for UART waiting
+  lda UART_LSR         ; Wait for UART to be ready
+  anda UARTF_LSR_THRE
+  bne 1B
+  stb UART_BUFR        ; Actually do our write
+  bra OUTSTR           ; Reset for the next char
+2                      ; Jump point for end of routine
+  rts
+
+  SECTION "Memtest"
+
+; RAM testing routine. Ported to 6809 from 6800, based on source for ROBIT-2 for
+; MIKBUG.
+RAMTEST
+  ldx #SRAM_BASE
+1                      ; Store 1 in memory
+  lda #1               ; Set [X] to 1
+  sta 0,x
+  cmpa 0,x             ; If failed print out an error indicator
+  bne 3F
+2                      ; Loop point for next address
+  asla                 ; Shift A and [X] left
+  asl 0,x
+  cmpa 0,x             ; Compare A and [X]
+  bne 3F
+  cmpa #$80            ; Only test up to $80
+  bne 2B               ; Loop if not $80
+  cmpx #$60FF          ; Compare X to end of RAM
+  beq 4F               ; Finish if we're at the end
+  leax 1,x             ; Increment X
+  bra 1B
+3                      ; Write out error indicator
+  ldb #'X
+  jsr OUTCHAR
+4                      ; Pass test
+  ldb #'P
+  jsr OUTCHAR
+  rts
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Interrupt and Reset Vectors
+;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+  SECTION "Vectors"
+  ORG VECS_BASE
+
+VECTORS
   fdb $0000 ; Reserved
   fdb $0000 ; SWI3
   fdb $0000 ; SWI2

code/boot/src/hardware.inc

@@ -0,0 +1,96 @@
+; CHIBI PC-09 Hardware Definitions
+; Copyright (c) 2024 Amber Zeller, Gale Faraday
+; Licensed under MIT
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Hardware Base Addresses
+;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+SRAM_BASE EQU $0000 ; SRAM Base Address
+UART_BASE EQU $7F00 ; UART Base Address
+ROM_BASE  EQU $8000 ; ROM Base Address and Entry Point
+VECS_BASE EQU $FFF0 ; Vectors Base Address
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; UART Registers and Flags
+;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; When UARTF_LCR_DLAB = 0:
+UART_BUFR EQU UART_BASE    ; TX/RX Buffer (Read for RX, Write for TX)
+UART_RBR EQU UART_BASE     ; RX Buffer Register
+UART_THR EQU UART_BASE     ; TX Holding Register
+UART_IER EQU UART_BASE + 1 ; Interrupt Enable Register
+
+; When UARTF_LCR_DLAB = 1:
+UART_DLL EQU UART_BASE     ; Divisor Latch (LSB)
+UART_DLM EQU UART_BASE + 1 ; Divisor Latch (MSB)
+
+; Independent of DLAB:
+UART_IIR EQU UART_BASE + 2 ; Interrupt Ident Register (Upon Read)
+UART_FCR EQU UART_BASE + 2 ; FIFO Control Register (Upon Write)
+UART_LCR EQU UART_BASE + 3 ; Line Control Register
+UART_MCR EQU UART_BASE + 4 ; MODEM Control Register
+UART_LSR EQU UART_BASE + 5 ; Line Status Register
+UART_MSR EQU UART_BASE + 6 ; MODEM Status Register
+UART_SCR EQU UART_BASE + 7 ; Scratch Register (Not for control just spare RAM)
+
+; UART Flags for Interrupt Enable Register:
+UARTF_IER_ERBFI EQU %10000000 ; Enable Received Data Available Interrupt
+UARTF_IER_ETBEI EQU %01000000 ; Enable Transmitter Holding Register Empty Interrupt
+UARTF_IER_ELSI  EQU %00100000 ; Enable Receiver Line Status Interrupt
+UARTF_IER_EDSSI EQU %00010000 ; Enable MODEM Status Interrupt
+
+; UART Flags for FIFO Control Register:
+UARTF_FCR_FE   EQU %10000000 ; FIFO Enabled
+UARTF_FCR_RFR  EQU %01000000 ; RCVR FIFO Reset
+UARTF_FCR_XFR  EQU %00100000 ; XMIT FIFO Reset
+UARTF_FCR_DMS  EQU %00010000 ; DMA Mode Select
+UARTF_FCR_RTL  EQU %00000010 ; RCVR Trigger (LSB)
+UARTF_FCR_RTM  EQU %00000001 ; RCVR Trigger (MSB)
+
+; UART Flags for Interrupt Ident Register:
+UARTF_IIR_INP  EQU %10000000 ; Reset if Interrupt Pending; 'INP' = Interrupt Not Pending
+UARTF_IIR_IIDM EQU %01110000 ; Interrupt ID Mask
+UARTF_IIR_FEM  EQU %00000011 ; FIFOs Enabled Mask
+
+; UART Flags for Line Control Register:
+UARTF_LCR_WLS  EQU %11000000 ; Word Length Select Bits
+UARTF_LCR_STB  EQU %00100000 ; Stop Bits
+UARTF_LCR_PEN  EQU %00010000 ; Parity Enable
+UARTF_LCR_EPS  EQU %00001000 ; Even Parity Select
+UARTF_LCR_SPR  EQU %00000100 ; Stick Parity
+UARTF_LCR_BRK  EQU %00000010 ; Set Break
+UARTF_LCR_DLAB EQU %00000001 ; Divisor Latch Access Bit
+
+; UART Flags for MODEM Control Register:
+UARTF_MCR_DTR  EQU %10000000 ; Data Terminal Ready
+UARTF_MCR_RTS  EQU %01000000 ; Enabling Request to Send
+UARTF_MCR_OUT1 EQU %00100000 ; Out 1
+UARTF_MCR_OUT2 EQU %00010000 ; Out 2
+UARTF_MCR_LOOP EQU %00001000 ; Loop
+
+; UART Flags for Line Status Register:
+UARTF_LSR_DR   EQU %10000000 ; Data Ready
+UARTF_LSR_OE   EQU %01000000 ; Overrun Error
+UARTF_LSR_PE   EQU %00100000 ; Parity Error
+UARTF_LSR_FE   EQU %00010000 ; Framing Error
+UARTF_LSR_BI   EQU %00001000 ; Break Interrupt
+UARTF_LSR_THRE EQU %00000100 ; Transmitter Holding Register
+UARTF_LSR_TEMT EQU %00000010 ; Transmitter Empty
+UARTF_LSR_FIFO EQU %00000001 ; Error in RCVR FIFO
+
+; UART Flags for MODEM Status Register:
+UARTF_MSR_DCTS EQU %10000000 ; Delta Clear to Send
+UARTF_MSR_DDSR EQU %01000000 ; Delta Data Set Ready
+UARTF_MSR_TERI EQU %00100000 ; Trailing Edge Ring Indicator
+UARTF_MSR_DDCD EQU %00010000 ; Delta Data Carrier Detect
+UARTF_MSR_CTS  EQU %00001000 ; Clear To Send
+UARTF_MSR_DSR  EQU %00000100 ; Data Set Ready
+UARTF_MSR_RI   EQU %00000010 ; Ring Indicator
+UARTF_MSR_DCD  EQU %00000001 ; Data Carrier Detect
+
+; vim: ft=asm

docs/6809-sn74ls612_timing.md

@@ -1,37 +0,0 @@
-# Motorola 6809 and TI SN74LS612 Timing
-
-## Motorola 6809 Timing
-Dual phase clock, E and Q. Staggered by half a clock. 
-1, 1.5, or 2 mHz. Nanosecond timing will be listed for all 3 speeds.
-
-* On Q rise, address and R/-W output is valid.
-* On E rise, data output is valid.
-* Time between Q rise and E rise is (approx) minimum 200/130/80ns and max 250/166/125ns.
-	* Time between address and R/-W output to data output.
-* On E fall, data input is read. Address and R/-W output become invalid.
-	* Data input must be valid for minimum 80/60/40ns before E fall.
-	* Output data on Q fall to ensure data input is valid.
-
-## TI SN74LS612 Timing
-Async
-
-### Write mode:
-
-* -Strobe occurs to perform write.
-* -Strobe pulse must be at least 75ns.
-* Data must be valid 75ns before -strobe fall.
-* -CS, R/-W, RS must be low at least 20ns before -strobe fall.
-* -CS, R/-W, RS, Data must be valid at least 20ns after -strobe rise.
-
-## Interface
-
-### 6809 Write to SN74LS612
-
-
-
-
-## Sources
-
-* Motorola MC6809 Datasheet, undated
-* Motorola MC6809E Datasheet, 1984
-* TI SN54LS610, SN54LS612, SN74LS610 THRU SN74LS613 Datasheet, 1981-1988

docs/jameco.txt

@@ -1,14 +0,0 @@
-RAM:
-https://www.jameco.com/z/HM62256LP-70-Major-Brands-IC-62256LP-70-Low-Power-CMOS-SRAM-256K-Bit-32Kx8-70ns_82472.html
-
-UART:
-https://www.jameco.com/z/PC16550DN-Major-Brands-Universal-Asynchronous-Receiver-Transmitter-with-FIFOs-DIP-40_27596.html
-
-Not available on Jameco: HD63C09, 28C256, uPD72020, VT82C42, 74LS612.
-eBay may be a better choice.
-
-12Mhz Passive Crystal 20pf:
-https://www.jameco.com/z/TQR49S12M0000A2040-Jameco-ValuePro-12-000MHz-HC49-Us-20pF-Crystal_325198.html
-
-1.8432 MHz Full Can Crystal Oscillator:
-https://www.jameco.com/z/MX045-3C-1M843200-JVP-Jameco-ValuePro-1-8432-MHz-Full-Can-Crystal-Oscillator_27879.html

font/README.md

@@ -0,0 +1,3 @@
+# Font
+
+An 8x8 font. Also a 16x16 temp logo.