gfaraday/chibi-pc09
1
0
Fork 0
forked from amberisvibin/chibi-pc09
Code Pull Requests Activity

chore: migrated to asm6809

Browse Source
This commit is contained in:
Gale Misery Faraday
2024-11-21 18:08:17 -06:00
parent 7fb867d5fd
commit ed135ef614
2 changed files with 28 additions and 41 deletions
Download Patch File Download Diff File Expand all files Collapse all files

17
code/boot/makefile
View File

@@ -10,17 +10,14 @@
TARGET := boot.bin TARGET := boot.bin
SRCDIR := src/ SRCDIR := src/
BUILDDIR := build/ MAINSRC := $(SRCDIR)boot.s
SRCS := $(wildcard $(SRCDIR)*.s) SRCS := $(wildcard $(SRCDIR)*.s)
OBJS := $(patsubst $(SRCDIR)%.s,$(BUILDDIR)%.o,$(SRCS))
# ------------------------------------------------------------------------------ # ------------------------------------------------------------------------------
# Toolchain Definitions # Toolchain Definitions
# ------------------------------------------------------------------------------ # ------------------------------------------------------------------------------
AS := lwasm AS := asm6809
LD := lwlink
AR := lwar
# ------------------------------------------------------------------------------ # ------------------------------------------------------------------------------
# Rules and Phony Targets # Rules and Phony Targets
@@ -28,12 +25,8 @@ AR := lwar
all: $(TARGET) all: $(TARGET)
$(TARGET): $(OBJS) $(TARGET): $(SRCS)
$(LD) -s boot.ld -o $@ $< $(AS) -o $(TARGET) $(MAINSRC)
$(OBJS): $(BUILDDIR)%.o : $(SRCDIR)%.s
-@mkdir -p $(BUILDDIR)
$(AS) --obj -o $@ $<
clean: clean:
rm -rvf $(BUILDDIR) $(TARGET) rm -v $(TARGET)

52
code/boot/src/boot.s
View File

@@ -2,28 +2,26 @@
; (Copyright (c) 2024 Amber Zeller ; (Copyright (c) 2024 Amber Zeller
; UART registers ; UART registers
UART = $7F00 UART EQU $7F00
; When DLAB = 0 ; When DLAB = 0:
BUFR = UART ; TX/RX Buffer (Read for RX, Write for TX) BUFR EQU UART ; TX/RX Buffer (Read for RX, Write for TX)
IER = UART+1 ; Interrupt Enable Register IER EQU UART+1 ; Interrupt Enable Register
IIR = UART+1 ; Interrupt Enable Register (Upon Read) IIR EQU UART+1 ; Interrupt Enable Register (Upon Read)
; When DLAB = 1 ; When DLAB = 1
DLL = UART ; Divisor Latch (LSB) DLL EQU UART ; Divisor Latch (LSB)
DLM = UART+1 ; Divisor Latch (MSB) DLM EQU UART+1 ; Divisor Latch (MSB)
FCR = UART+2 ; FIFO Control Register (Upon Write) FCR EQU UART+2 ; FIFO Control Register (Upon Write)
LCR = UART+3 ; Line Control Register LCR EQU UART+3 ; Line Control Register
MCR = UART+4 ; MODEM Control Register MCR EQU UART+4 ; MODEM Control Register
LSR = UART+5 ; Line Status Register LSR EQU UART+5 ; Line Status Register
MSR = UART+6 ; MODEM Status Register MSR EQU UART+6 ; MODEM Status Register
SCR = UART+7 ; Scratch Register (Not for control just spare RAM) SCR EQU UART+7 ; Scratch Register (Not for control just spare RAM)
; SECTION code
ORG $8000 ORG $8000
RESET: RESET
; UART Setup ; UART Setup
lda %11000001 ; 8n1 serial, enable DLAB lda %11000001 ; 8n1 serial, enable DLAB
sta LCR sta LCR
@@ -40,19 +38,15 @@ RESET:
sta MCR sta MCR
lda 'H ; send H lda 'H ; send H
STA BUFR sta BUFR
; ENDSECTION
; SECTION vectors
ORG $FFF0 ORG $FFF0
; Reset/Interrupt Vectors ; Reset/Interrupt Vectors
fdb $0000 ; Reserved fdb $0000 ; Reserved
fdb $0000 ; SWI3 fdb $0000 ; SWI3
fdb $0000 ; SWI2 fdb $0000 ; SWI2
fdb $0000 ; FIRQ fdb $0000 ; FIRQ
fdb $0000 ; IRQ fdb $0000 ; IRQ
fdb $0000 ; SWI fdb $0000 ; SWI
fdb $0000 ; NMI fdb $0000 ; NMI
fdb RESET ; Reset fdb RESET ; Reset
; ENDSECTION