From cc8a9fc95fb1e73887c0e90b90e3f14f17ba20da Mon Sep 17 00:00:00 2001 From: Gale Faraday Date: Tue, 2 Sep 2025 16:46:45 -0500 Subject: [PATCH] feat(boot): new stack initialization routine --- code/boot/src/hardware.inc | 10 ++++++++++ code/boot/src/reset.s | 20 +++++++++++++++++--- 2 files changed, 27 insertions(+), 3 deletions(-) diff --git a/code/boot/src/hardware.inc b/code/boot/src/hardware.inc index fcbe629..01e96b1 100644 --- a/code/boot/src/hardware.inc +++ b/code/boot/src/hardware.inc @@ -15,6 +15,16 @@ UART_BASE EQU $7F00 ; UART Base Address ROM_BASE EQU $8000 ; ROM Base Address and Entry Point VECS_BASE EQU $FFF0 ; Vectors Base Address +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Stack Base Address and Size Information +;; +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +STACK_BOTTOM EQU $0100 ; Bottom address of system stack +STACK_DEPTH EQU $FF ; System stack's depth +STACK_TOP EQU STACK_BOTTOM+STACK_DEPTH ; Top address of system stack + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; UART Registers and Flags diff --git a/code/boot/src/reset.s b/code/boot/src/reset.s index 32a96a1..afc3c4b 100644 --- a/code/boot/src/reset.s +++ b/code/boot/src/reset.s @@ -16,8 +16,21 @@ EXPORT RESET RESET + +CLRSTACK + ; Initialize the system stack + lda #$00 ; Initialize A & X to zero out the stack + ldx #$0000 +NEXT@ + sta STACK_BOTTOM,x ; Write a zero and progress to the next byte + leax 1,x + cmpx #STACK_DEPTH ; See if we're at the top of the stack yet + blo NEXT@ ; Loop if we aren't at the end yet + lds STACK_TOP ; Set S to top of newly cleared stack + +SERINIT ; 8n1 Serial Enable DLAB - lda #UARTF_LCR_WLS | UARTF_LCR_DLAB + lda #UARTF_LCR_WLS|UARTF_LCR_DLAB sta UART_LCR ; REVIEW: Potential endianness hiccough here ldd #$0C00 ; Set divisor to 12 (9600 baud) @@ -29,7 +42,8 @@ RESET sta UART_MCR lda #'H ; send 'H' sta UART_BUFR -WAIT@ + +WAIT sync ; Wait for interrupts nop - bra WAIT@ + bra WAIT