forked from amberisvibin/chibi-pc09
chore: renamed source file to move it to src dir
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58
code/boot/src/boot.s
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58
code/boot/src/boot.s
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; CHIBI PC-09 Prototype #1 Boot ROM
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; (Copyright (c) 2024 Amber Zeller
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; UART registers
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UART = $7F00
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; When DLAB = 0
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BUFR = UART ; TX/RX Buffer (Read for RX, Write for TX)
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IER = UART+1 ; Interrupt Enable Register
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IIR = UART+1 ; Interrupt Enable Register (Upon Read)
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; When DLAB = 1
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DLL = UART ; Divisor Latch (LSB)
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DLM = UART+1 ; Divisor Latch (MSB)
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FCR = UART+2 ; FIFO Control Register (Upon Write)
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LCR = UART+3 ; Line Control Register
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MCR = UART+4 ; MODEM Control Register
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LSR = UART+5 ; Line Status Register
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MSR = UART+6 ; MODEM Status Register
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SCR = UART+7 ; Scratch Register (Not for control just spare RAM)
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; SECTION code
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ORG $8000
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RESET:
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; UART Setup
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lda %11000001 ; 8n1 serial, enable DLAB
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sta LCR
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lda $00 ; Set divisor to 12 (9600 baud)
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sta DLL
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lda $0C
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sta DLM
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lda %11000000 ; 8n1 serial, disable DLAB
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sta LCR
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lda %01000000 ; Enable RTS
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sta MCR
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lda 'H ; send H
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STA BUFR
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; ENDSECTION
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; SECTION vectors
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ORG $FFF0
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; Reset/Interrupt Vectors
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fdb $0000 ; Reserved
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fdb $0000 ; SWI3
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fdb $0000 ; SWI2
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fdb $0000 ; FIRQ
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fdb $0000 ; IRQ
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fdb $0000 ; SWI
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fdb $0000 ; NMI
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fdb RESET ; Reset
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; ENDSECTION
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