diff --git a/code/boot/linkscript b/code/boot/linkscript new file mode 100644 index 0000000..e36add1 --- /dev/null +++ b/code/boot/linkscript @@ -0,0 +1,5 @@ +section RESET load 8000 +section SERIAL +section MEMTEST + +section VECTORS high 100000 diff --git a/code/boot/makefile b/code/boot/makefile index e7f03d3..b6207fa 100644 --- a/code/boot/makefile +++ b/code/boot/makefile @@ -8,26 +8,45 @@ # Project Defaults & Folders # ------------------------------------------------------------------------------ -TARGET := boot.bin +TARGET := boot +TARGROM := $(TARGET).bin SRCDIR := src/ -MAINSRC := $(SRCDIR)boot.s +BUILDDIR := build/ SRCS := $(wildcard $(SRCDIR)*.s) +OBJS := $(patsubst $(SRCDIR)%.s,$(BUILDDIR)%.o,$(SRCS)) INCS := $(wildcard $(SRCDIR)*.inc) # ------------------------------------------------------------------------------ # Toolchain Definitions # ------------------------------------------------------------------------------ -AS := asm6809 +AS := lwasm +LD := lwlink +FIX := mot2bin + +ASFLAGS := -f obj +LDFLAGS := -f srec -m map.txt -s linkscript # ------------------------------------------------------------------------------ # Rules and Phony Targets # ------------------------------------------------------------------------------ -all: $(TARGET) +all: $(TARGROM) -$(TARGET): $(SRCS) $(INCS) - $(AS) -o $(TARGET) $(MAINSRC) +# Fix srec into flashable bin file +$(TARGROM): $(TARGET).s19 + $(FIX) -out $@ $< +# Link objects +$(TARGET).s19: $(OBJS) + $(LD) $(LDFLAGS) -o $@ $^ + +# Assemble objects +$(OBJS): $(BUILDDIR)%.o : $(SRCDIR)%.s + -@mkdir -p $(BUILDDIR) + $(AS) $(ASFLAGS) -o $@ $< + +.IGNORE: clean clean: - rm -v $(TARGET) + @echo 'Cleaning up intermediary files...' + @rm -rv $(TARGROM) $(TARGET).s19 $(BUILDDIR) diff --git a/code/boot/src/boot.s b/code/boot/src/boot.s deleted file mode 100644 index 408ced3..0000000 --- a/code/boot/src/boot.s +++ /dev/null @@ -1,118 +0,0 @@ -; CHIBI PC-09 Prototype #1 Boot ROM -- Hardware Initialization and Reset Vecs -; Copyright (c) 2024 Amber Zeller, Gale Faraday -; Licensed under MIT - - INCLUDE "src/hardware.inc" - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Hardware Initialization Routines -;; -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - - SECTION "Reset" - ORG ROM_BASE - -RESET - ; 8n1 Serial Enable DLAB - lda #(UARTF_LCR_WLS | UARTF_LCR_DLAB) - sta UART_LCR - - ; REVIEW: Potential endianness hiccough here - ldd #$0C00 ; Set divisor to 12 (9600 baud) - sta UART_DLM - stb UART_DLL - - lda #(UARTF_LCR_WLS) ; 8n1 serial, disable DLAB - sta UART_LCR - - lda #(UARTF_MCR_RTS) ; Enable Request-to-Send - sta UART_MCR - - lda 'H ; send 'H' - sta UART_BUFR - -WAIT - sync ; Wait for interrupts - nop - bra WAIT - - SECTION "Serial" - -; Writes a char to the UART in non FIFO mode, preserves A. -; @param b: char to write -OUTCHAR - pshs a ; Preserve A -1 - lda UART_LSR ; if LSR.THRE == 1 then write - anda UARTF_LSR_THRE - bne 1B ; Loop if UART not ready yet - stb UART_BUFR ; Write char - puls a ; Restore A - rts - -; Writes a null terminated string to the UART in non FIFO mode, clobbers A and -; B. -; @param x: null terminated string start address. -OUTSTR - ldb x ; Get the next value from X - cmpb #$00 ; Make sure that mother is non-null - beq 2F - leax 1,x ; Increment X for our next char -1 ; Loop point for UART waiting - lda UART_LSR ; Wait for UART to be ready - anda UARTF_LSR_THRE - bne 1B - stb UART_BUFR ; Actually do our write - bra OUTSTR ; Reset for the next char -2 ; Jump point for end of routine - rts - - SECTION "Memtest" - -; RAM testing routine. Ported to 6809 from 6800, based on source for ROBIT-2 for -; MIKBUG. -RAMTEST - ldx #SRAM_BASE -1 ; Store 1 in memory - lda #1 ; Set [X] to 1 - sta 0,x - cmpa 0,x ; If failed print out an error indicator - bne 3F -2 ; Loop point for next address - asla ; Shift A and [X] left - asl 0,x - cmpa 0,x ; Compare A and [X] - bne 3F - cmpa #$80 ; Only test up to $80 - bne 2B ; Loop if not $80 - cmpx #$60FF ; Compare X to end of RAM - beq 4F ; Finish if we're at the end - leax 1,x ; Increment X - bra 1B -3 ; Write out error indicator - ldb #'X - jsr OUTCHAR -4 ; Pass test - ldb #'P - jsr OUTCHAR - rts - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Interrupt and Reset Vectors -;; -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - - SECTION "Vectors" - ORG VECS_BASE - -VECTORS - fdb $0000 ; Reserved - fdb $0000 ; SWI3 - fdb $0000 ; SWI2 - fdb $0000 ; FIRQ - fdb $0000 ; IRQ - fdb $0000 ; SWI - fdb $0000 ; NMI - fdb RESET ; Reset diff --git a/code/boot/src/hardware.inc b/code/boot/src/hardware.inc index 0049d02..fcbe629 100644 --- a/code/boot/src/hardware.inc +++ b/code/boot/src/hardware.inc @@ -1,7 +1,9 @@ ; CHIBI PC-09 Hardware Definitions -; Copyright (c) 2024 Amber Zeller, Gale Faraday +; Copyright (c) 2024-2025 Amber Zeller, Gale Faraday ; Licensed under MIT +; vim: ft=asm + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Hardware Base Addresses @@ -20,23 +22,23 @@ VECS_BASE EQU $FFF0 ; Vectors Base Address ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; When UARTF_LCR_DLAB = 0: -UART_BUFR EQU UART_BASE ; TX/RX Buffer (Read for RX, Write for TX) -UART_RBR EQU UART_BASE ; RX Buffer Register -UART_THR EQU UART_BASE ; TX Holding Register -UART_IER EQU UART_BASE + 1 ; Interrupt Enable Register +UART_BUFR EQU UART_BASE ; TX/RX Buffer (Read for RX, Write for TX) +UART_RBR EQU UART_BASE ; RX Buffer Register +UART_THR EQU UART_BASE ; TX Holding Register +UART_IER EQU UART_BASE+1 ; Interrupt Enable Register ; When UARTF_LCR_DLAB = 1: -UART_DLL EQU UART_BASE ; Divisor Latch (LSB) -UART_DLM EQU UART_BASE + 1 ; Divisor Latch (MSB) +UART_DLL EQU UART_BASE ; Divisor Latch (LSB) +UART_DLM EQU UART_BASE+1 ; Divisor Latch (MSB) ; Independent of DLAB: -UART_IIR EQU UART_BASE + 2 ; Interrupt Ident Register (Upon Read) -UART_FCR EQU UART_BASE + 2 ; FIFO Control Register (Upon Write) -UART_LCR EQU UART_BASE + 3 ; Line Control Register -UART_MCR EQU UART_BASE + 4 ; MODEM Control Register -UART_LSR EQU UART_BASE + 5 ; Line Status Register -UART_MSR EQU UART_BASE + 6 ; MODEM Status Register -UART_SCR EQU UART_BASE + 7 ; Scratch Register (Not for control just spare RAM) +UART_IIR EQU UART_BASE+2 ; Interrupt Ident Register (Upon Read) +UART_FCR EQU UART_BASE+2 ; FIFO Control Register (Upon Write) +UART_LCR EQU UART_BASE+3 ; Line Control Register +UART_MCR EQU UART_BASE+4 ; MODEM Control Register +UART_LSR EQU UART_BASE+5 ; Line Status Register +UART_MSR EQU UART_BASE+6 ; MODEM Status Register +UART_SCR EQU UART_BASE+7 ; Scratch Register (Not for control just spare RAM) ; UART Flags for Interrupt Enable Register: UARTF_IER_ERBFI EQU %10000000 ; Enable Received Data Available Interrupt @@ -93,4 +95,3 @@ UARTF_MSR_DSR EQU %00000100 ; Data Set Ready UARTF_MSR_RI EQU %00000010 ; Ring Indicator UARTF_MSR_DCD EQU %00000001 ; Data Carrier Detect -; vim: ft=asm diff --git a/code/boot/src/memtest.s b/code/boot/src/memtest.s new file mode 100644 index 0000000..8c1cdc4 --- /dev/null +++ b/code/boot/src/memtest.s @@ -0,0 +1,42 @@ +; CHIBI PC-09 Prototype #1 Boot ROM -- Memory Testing Routines +; Copyright (c) 2024-2025 Amber Zeller, Gale Faraday +; Licensed under MIT + + INCLUDE "hardware.inc" + INCLUDE "serial.inc" + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Memory Testing Routines +;; +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + + SECTION MEMTEST + +; RAM testing routine. Ported to 6809 from 6800, based on source for ROBIT-2 for +; MIKBUG. +RAMTEST + ldx #SRAM_BASE +AGAIN@ ; Store 1 in memory + lda #1 ; Set [X] to 1 + sta 0,x + cmpa 0,x ; If failed print out an error indicator + bne ERR@ +NEXT@ ; Loop point for next address + asla ; Shift A and [X] left + asl 0,x + cmpa 0,x ; Compare A and [X] + bne ERR@ + cmpa #$80 ; Only test up to $80 + bne NEXT@ ; Loop if not $80 + cmpx #$60FF ; Compare X to end of RAM + beq PASS@ ; Finish if we're at the end + leax 1,x ; Increment X + bra AGAIN@ +ERR@ ; Write out error indicator + ldb #'X + jsr OUTCHAR +PASS@ ; Pass test + ldb #'P + jsr OUTCHAR + rts diff --git a/code/boot/src/reset.inc b/code/boot/src/reset.inc new file mode 100644 index 0000000..cde2374 --- /dev/null +++ b/code/boot/src/reset.inc @@ -0,0 +1,7 @@ +; CHIBI PC-09 Prototype #1 -- Reset Handler Header +; Copyright (c) 2025 Amber Zeller, Gale Faraday +; Licensed under MIT + +; vim: ft=asm + +RESET IMPORT diff --git a/code/boot/src/reset.s b/code/boot/src/reset.s new file mode 100644 index 0000000..32a96a1 --- /dev/null +++ b/code/boot/src/reset.s @@ -0,0 +1,35 @@ +; CHIBI PC-09 Prototype #1 Boot ROM -- Reset Handler +; Copyright (c) 2024-2025 Amber Zeller, Gale Faraday +; Licensed under MIT + + INCLUDE "hardware.inc" + INCLUDE "serial.inc" + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Hardware Initialization Routines +;; +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + + SECTION RESET + + EXPORT RESET + +RESET + ; 8n1 Serial Enable DLAB + lda #UARTF_LCR_WLS | UARTF_LCR_DLAB + sta UART_LCR + ; REVIEW: Potential endianness hiccough here + ldd #$0C00 ; Set divisor to 12 (9600 baud) + sta UART_DLM + stb UART_DLL + lda #(UARTF_LCR_WLS) ; 8n1 serial, disable DLAB + sta UART_LCR + lda #(UARTF_MCR_RTS) ; Enable Request-to-Send + sta UART_MCR + lda #'H ; send 'H' + sta UART_BUFR +WAIT@ + sync ; Wait for interrupts + nop + bra WAIT@ diff --git a/code/boot/src/serial.inc b/code/boot/src/serial.inc new file mode 100644 index 0000000..64c4f60 --- /dev/null +++ b/code/boot/src/serial.inc @@ -0,0 +1,8 @@ +; CHIBI PC-09 Prototype #1 -- Serial Driver Header +; Copyright (c) 2025 Amber Zeller, Gale Faraday +; Licensed under MIT + +; vim: ft=asm + +OUTCHAR IMPORT +OUTSTR IMPORT diff --git a/code/boot/src/serial.s b/code/boot/src/serial.s new file mode 100644 index 0000000..f43d2d9 --- /dev/null +++ b/code/boot/src/serial.s @@ -0,0 +1,45 @@ +; CHIBI PC-09 Prototype #1 Boot ROM -- Serial Driver +; Copyright (c) 2024-2025 Amber Zeller, Gale Faraday +; Licensed under MIT + + INCLUDE "hardware.inc" + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Serial UART Driver +;; +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + + SECTION SERIAL + + EXPORT OUTCHAR + EXPORT OUTSTR + +; Writes a char to the UART in non FIFO mode, preserves A. +; @param b: char to write +OUTCHAR + pshs a ; Preserve A +NOTREADY@ + lda UART_LSR ; if LSR.THRE == 1 then write + anda UARTF_LSR_THRE + bne NOTREADY@ ; Loop if UART not ready yet + stb UART_BUFR ; Write char + puls a ; Restore A + rts + +; Writes a null terminated string to the UART in non FIFO mode, clobbers A and +; B. +; @param x: null terminated string start address. +OUTSTR + ldb 0,x ; Get the next value from X + cmpb #$00 ; Make sure that we aren't at a terminator + beq END@ + leax 1,x ; Increment X for our next char +NOTREADY@ ; Loop point for UART waiting + lda UART_LSR ; Wait for UART to be ready + anda UARTF_LSR_THRE + bne NOTREADY@ + stb UART_BUFR ; Actually do our write + bra OUTSTR ; Reset for the next char +END@ ; Jump point for end of routine + rts diff --git a/code/boot/src/vecs.s b/code/boot/src/vecs.s new file mode 100644 index 0000000..3162a2c --- /dev/null +++ b/code/boot/src/vecs.s @@ -0,0 +1,23 @@ +; CHIBI PC-09 Prototype #1 Boot ROM -- Interrupt and Reset Vectors +; Copyright (c) 2024-2025 Amber Zeller, Gale Faraday +; Licensed under MIT + + INCLUDE "reset.inc" + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Interrupt and Reset Vectors +;; +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + + SECTION VECTORS + +VECTORS + fdb $0000 ; Reserved + fdb $0000 ; SWI3 + fdb $0000 ; SWI2 + fdb $0000 ; FIRQ + fdb $0000 ; IRQ + fdb $0000 ; SWI + fdb $0000 ; NMI + fdb RESET ; Reset