update readme to reflect changes

Setup hardware.inc

README.md

@@ -1,17 +1,17 @@
 # chibi pc-09
-![GitHub last commit](https://img.shields.io/github/last-commit/amberisvibin/chibi-pc80)
+![GitHub last commit](https://img.shields.io/github/last-commit/amberisvibin/chibi-pc09)
 
 ## Description
 
-The PC-09 will be a 6309 based microcomputer with a 74LS612 MMU, uPD72020 graphics, PS/2 keyboard and mouse input, and a capable UART. 
+The PC-09 will be a 6309 based microcomputer with an MMU using 74HC670 register files and dual 16550 UARTs. The plan is to eventually add uPD7220 graphics and PS/2 mouse and keyboard.
 
-The MMU will allow up to 2 megabytes of I/O to be paged into the address space. Pages are 4k. System storage will be paged into the address space as well, as it will be either EEPROM or flash. 
+The two 74HC670s will take the top 4 bits of the address bus and expand them to 8 bits, turning the 16 bit cpu address space into a 20 bit address space capable of addressing 1MB of memory. Memory pages are 4KB. Being a register file, any page can be mapped to any slot, allowing complex memory management schemes.
 
-The uPD72020 is a very advanced graphics chip for it's time, capable of accelerated drawing of lines, shapes, fills, and characters. It can be coerced into outputting a VGA signal at 640x480 and *maybe* 800x600. 
+The 16550 UART is capable of interrupt driven operation with FIFOs, allowing for characters to be processed in batches rather than individually, minimizing task switch delays. They also support hardware flow control, and some versions can automatically assert RTS when the FIFO is nearing full.
 
-Keyboard and mouse will be handled by the VIA VT82C42. It is an Intel 8242 compatible controller capable of both PS/2 keyboard and mouse. It's interface is relatively simple, which makes connection easy. It relies on interrupts, so an interrupt system will be required.
+The uPD7220 graphics are very powerful, allowing 16 colors at 640x480, but it is a complex chip to get working. It will be left for a later date.
 
-To avoid the infamous 65C22 bug, the system will use the 16550 UART from the PC ecosystem. It is *relatively* easy to interface this to a 6800 style bus. It has more features than a 65C22 as well. As configured, it will be stable up to 38,400 baud. 
+The solution for PS/2 keyboard and mouse have not yet been decided.
 
 ## Progress
 
@@ -21,6 +21,8 @@ Prototype 1 is currently in progress. It will be a much simpler system. It will
 
 The PCB and parts for Prototype #1 have been ordered, and assembly will begin soon. Initial test code is now available in the code/ directory.
 
+Assembly is in progress.
+
 ## License
 
 This project is licensed under the MIT license. This applies to both the hardware (schematics, bill of materials, pcb layouts) and documentation. This does *not* apply to the datasheets/ directory, the books/ directory or code/assist09/. Those files belong to their respective copyright holders.

code/boot/src/boot.s

@@ -13,25 +13,26 @@
   ORG ROM_BASE
 
 RESET
-  lda #%11000001 ; 8n1 serial, enable DLAB
+  ; 8n1 Serial Enable DLAB
+  lda #(UARTF_LCR_WLS | UARTF_LCR_DLAB)
   sta UART_LCR
 
-  lda #$00       ; Set divisor to 12 (9600 baud)
-  sta UART_DLL
-  lda #$0C
+  ; REVIEW: Potential endianness hiccough here
+  ldd #$0C00           ; Set divisor to 12 (9600 baud)
   sta UART_DLM
+  stb UART_DLL
 
-  lda #%11000000 ; 8n1 serial, disable DLAB
+  lda #(UARTF_LCR_WLS) ; 8n1 serial, disable DLAB
   sta UART_LCR
 
-  lda #%01000000 ; Enable RTS
+  lda #(UARTF_MCR_RTS) ; Enable Request-to-Send
   sta UART_MCR
 
-  lda 'H        ; send 'H'
+  lda 'H               ; send 'H'
   sta UART_BUFR
 
 WAIT
-  sync           ; Wait for interrupts
+  sync                 ; Wait for interrupts
   nop
   bra WAIT
 

code/boot/src/hardware.inc

@@ -19,14 +19,18 @@ VECS_BASE EQU $FFF0 ; Vectors Base Address
 ;;
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
-; When UARTF_DLAB = 0:
+; When UARTF_LCR_DLAB = 0:
 UART_BUFR EQU UART_BASE    ; TX/RX Buffer (Read for RX, Write for TX)
+UART_RBR EQU UART_BASE     ; RX Buffer Register
+UART_THR EQU UART_BASE     ; TX Holding Register
 UART_IER EQU UART_BASE + 1 ; Interrupt Enable Register
-UART_IIR EQU UART_BASE + 1 ; Interrupt Ident Register (Upon Read)
 
-; When UARTF_DLAB = 1:
+; When UARTF_LCR_DLAB = 1:
 UART_DLL EQU UART_BASE     ; Divisor Latch (LSB)
 UART_DLM EQU UART_BASE + 1 ; Divisor Latch (MSB)
+
+; Independent of DLAB:
+UART_IIR EQU UART_BASE + 2 ; Interrupt Ident Register (Upon Read)
 UART_FCR EQU UART_BASE + 2 ; FIFO Control Register (Upon Write)
 UART_LCR EQU UART_BASE + 3 ; Line Control Register
 UART_MCR EQU UART_BASE + 4 ; MODEM Control Register
@@ -34,8 +38,59 @@ UART_LSR EQU UART_BASE + 5 ; Line Status Register
 UART_MSR EQU UART_BASE + 6 ; MODEM Status Register
 UART_SCR EQU UART_BASE + 7 ; Scratch Register (Not for control just spare RAM)
 
-; UART Flags:
-UARTF_DLAB EQU %00000001   ; Divisor Latch Access Bit
-UARTF_8N1  EQU %11000000   ; 8n1 Serial Mode
+; UART Flags for Interrupt Enable Register:
+UARTF_IER_ERBFI EQU %10000000 ; Enable Received Data Available Interrupt
+UARTF_IER_ETBEI EQU %01000000 ; Enable Transmitter Holding Register Empty Interrupt
+UARTF_IER_ELSI  EQU %00100000 ; Enable Receiver Line Status Interrupt
+UARTF_IER_EDSSI EQU %00010000 ; Enable MODEM Status Interrupt
+
+; UART Flags for FIFO Control Register:
+UARTF_FCR_FE   EQU %10000000 ; FIFO Enabled
+UARTF_FCR_RFR  EQU %01000000 ; RCVR FIFO Reset
+UARTF_FCR_XFR  EQU %00100000 ; XMIT FIFO Reset
+UARTF_FCR_DMS  EQU %00010000 ; DMA Mode Select
+UARTF_FCR_RTL  EQU %00000010 ; RCVR Trigger (LSB)
+UARTF_FCR_RTM  EQU %00000001 ; RCVR Trigger (MSB)
+
+; UART Flags for Interrupt Ident Register:
+UARTF_IIR_INP  EQU %10000000 ; Reset if Interrupt Pending; 'INP' = Interrupt Not Pending
+UARTF_IIR_IIDM EQU %01110000 ; Interrupt ID Mask
+UARTF_IIR_FEM  EQU %00000011 ; FIFOs Enabled Mask
+
+; UART Flags for Line Control Register:
+UARTF_LCR_WLS  EQU %11000000 ; Word Length Select Bits
+UARTF_LCR_STB  EQU %00100000 ; Stop Bits
+UARTF_LCR_PEN  EQU %00010000 ; Parity Enable
+UARTF_LCR_EPS  EQU %00001000 ; Even Parity Select
+UARTF_LCR_SPR  EQU %00000100 ; Stick Parity
+UARTF_LCR_BRK  EQU %00000010 ; Set Break
+UARTF_LCR_DLAB EQU %00000001 ; Divisor Latch Access Bit
+
+; UART Flags for MODEM Control Register:
+UARTF_MCR_DTR  EQU %10000000 ; Data Terminal Ready
+UARTF_MCR_RTS  EQU %01000000 ; Enabling Request to Send
+UARTF_MCR_OUT1 EQU %00100000 ; Out 1
+UARTF_MCR_OUT2 EQU %00010000 ; Out 2
+UARTF_MCR_LOOP EQU %00001000 ; Loop
+
+; UART Flags for Line Status Register:
+UARTF_LSR_DR   EQU %10000000 ; Data Ready
+UARTF_LSR_OE   EQU %01000000 ; Overrun Error
+UARTF_LSR_PE   EQU %00100000 ; Parity Error
+UARTF_LSR_FE   EQU %00010000 ; Framing Error
+UARTF_LSR_BI   EQU %00001000 ; Break Interrupt
+UARTF_LSR_THRE EQU %00000100 ; Transmitter Holding Register
+UARTF_LSR_TEMT EQU %00000010 ; Transmitter Empty
+UARTF_LSR_FIFO EQU %00000001 ; Error in RCVR FIFO
+
+; UART Flags for MODEM Status Register:
+UARTF_MSR_DCTS EQU %10000000 ; Delta Clear to Send
+UARTF_MSR_DDSR EQU %01000000 ; Delta Data Set Ready
+UARTF_MSR_TERI EQU %00100000 ; Trailing Edge Ring Indicator
+UARTF_MSR_DDCD EQU %00010000 ; Delta Data Carrier Detect
+UARTF_MSR_CTS  EQU %00001000 ; Clear To Send
+UARTF_MSR_DSR  EQU %00000100 ; Data Set Ready
+UARTF_MSR_RI   EQU %00000010 ; Ring Indicator
+UARTF_MSR_DCD  EQU %00000001 ; Data Carrier Detect
 
 ; vim: ft=asm