minimum functional bootcode

code/boot/boot.s

@@ -5,28 +5,42 @@
 UART = $7F00
 
 ; When DLAB = 0
-BUFR = UART    ; TX/RX Buffer (Read for RX, Write for TX)
-IER = UART + 1 ; Interrupt Enable Register
-IIR = UART + 1 ; Interrupt Enable Register (Upon Read)
+BUFR = UART  ; TX/RX Buffer (Read for RX, Write for TX)
+IER = UART+1 ; Interrupt Enable Register
+IIR = UART+1 ; Interrupt Enable Register (Upon Read)
 ; When DLAB = 1
-DLL = UART     ; Divisor Latch (LSB)
-DLM = UART + 1 ; Divisor Latch (MSB)
+DLL = UART   ; Divisor Latch (LSB)
+DLM = UART+1 ; Divisor Latch (MSB)
 
-FCR = UART + 2 ; FIFO Control Register (Upon Write)
-LCR = UART + 3 ; Line Control Register
-MCR = UART + 4 ; MODEM Control Register
-LSR = UART + 5 ; Line Status Register
-MSR = UART + 6 ; MODEM Status Register
-SCR = UART + 7 ; Scratch Register (Not for control just spare RAM)
+FCR = UART+2 ; FIFO Control Register (Upon Write)
+LCR = UART+3 ; Line Control Register
+MCR = UART+4 ; MODEM Control Register
+LSR = UART+5 ; Line Status Register
+MSR = UART+6 ; MODEM Status Register
+SCR = UART+7 ; Scratch Register (Not for control just spare RAM)
 
 ;  SECTION code
 
   org $8000
 
 RESET:
-  sta $cc
-  jmp RESET
-  fdb RESET
+  ; UART Setup
+  lda %11000001 ; 8n1 serial, enable DLAB
+  sta LCR
+
+  lda $00       ; Set divisor to 12 (9600 baud)
+  sta DLL
+  lda $0C
+  sta DLM
+
+  lda %11000000 ; 8n1 serial, disable DLAB
+  sta LCR
+
+  lda %01000000 ; Enable RTS
+  sta MCR
+
+  lda 'H        ; send H
+  STA BUFR
 
 ;  ENDSECTION
 

code/boot/boot.s19

@@ -1,5 +1,6 @@
 S01800005B6C77746F6F6C7320342E32335D20626F6F742E73BF
-S10A800097CC7E8000800094
+S113800096C1B77F039600B77F00960CB77F0196A1
+S1118010C0B77F039640B77F049648B77F0041
 S113FFF0000000000000000000000000000080007D
-S5030002FA
+S5030003F9
 S9030000FC