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refactor: made preparations for hardware.inc.

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This commit is contained in:
Gale Misery Faraday
2024-11-28 11:07:22 -06:00
parent 89218accd0
commit 91286a143d
1 changed files with 28 additions and 27 deletions
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55
code/boot/src/boot.s
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@@ -1,48 +1,49 @@
; CHIBI PC-09 Prototype #1 Boot ROM ; CHIBI PC-09 Prototype #1 Boot ROM -- Hardware Initialization and Reset Vecs
; Copyright (c) 2024 Amber Zeller ; Copyright (c) 2024 Amber Zeller, Gale Faraday
; Licensed under MIT ; Licensed under MIT
; UART registers INCLUDE "hardware.inc"
UART EQU $7F00
; When DLAB = 0: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
BUFR EQU UART ; TX/RX Buffer (Read for RX, Write for TX) ;;
IER EQU UART + 1 ; Interrupt Enable Register ;; Hardware Initialization Routines
IIR EQU UART + 1 ; Interrupt Ident Register (Upon Read) ;;
; When DLAB = 1 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
DLL EQU UART ; Divisor Latch (LSB)
DLM EQU UART + 1 ; Divisor Latch (MSB)
FCR EQU UART + 2 ; FIFO Control Register (Upon Write)
LCR EQU UART + 3 ; Line Control Register
MCR EQU UART + 4 ; MODEM Control Register
LSR EQU UART + 5 ; Line Status Register
MSR EQU UART + 6 ; MODEM Status Register
SCR EQU UART + 7 ; Scratch Register (Not for control just spare RAM)
ORG $8000 ORG $8000
RESET RESET
; UART Setup
lda %11000001 ; 8n1 serial, enable DLAB lda %11000001 ; 8n1 serial, enable DLAB
sta LCR sta UART_LCR
lda $00 ; Set divisor to 12 (9600 baud) lda $00 ; Set divisor to 12 (9600 baud)
sta DLL sta UART_DLL
lda $0C lda $0C
sta DLM sta UART_DLM
lda %11000000 ; 8n1 serial, disable DLAB lda %11000000 ; 8n1 serial, disable DLAB
sta LCR sta UART_LCR
lda %01000000 ; Enable RTS lda %01000000 ; Enable RTS
sta MCR sta UART_MCR
lda 'H ; send H lda 'H ; send 'H'
sta BUFR sta UART_BUFR
WAIT
sync ; Wait for interrupts
nop
bra WAIT
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Interrupt and Reset Vectors
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
ORG $FFF0 ORG $FFF0
; Reset/Interrupt Vectors
VECTORS
fdb $0000 ; Reserved fdb $0000 ; Reserved
fdb $0000 ; SWI3 fdb $0000 ; SWI3
fdb $0000 ; SWI2 fdb $0000 ; SWI2