copy all local files to repo
cp/m files, sprites, circuit design
This commit is contained in:
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(module "DIP762W55P254L2642H457Q20N" (layer F.Cu)
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(descr "CASE 738–03")
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(tags "Integrated Circuit")
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(fp_text reference IC** (at 0 0) (layer F.SilkS)
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(effects (font (size 1.27 1.27) (thickness 0.254)))
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)
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(fp_text user %R (at 0 0) (layer F.Fab)
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(effects (font (size 1.27 1.27) (thickness 0.254)))
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)
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(fp_text value "DIP762W55P254L2642H457Q20N" (at 0 0) (layer F.SilkS) hide
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(effects (font (size 1.27 1.27) (thickness 0.254)))
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)
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(fp_line (start -4.635 -13.835) (end 4.635 -13.835) (layer F.CrtYd) (width 0.05))
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(fp_line (start 4.635 -13.835) (end 4.635 13.835) (layer F.CrtYd) (width 0.05))
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(fp_line (start 4.635 13.835) (end -4.635 13.835) (layer F.CrtYd) (width 0.05))
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(fp_line (start -4.635 13.835) (end -4.635 -13.835) (layer F.CrtYd) (width 0.05))
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(fp_line (start -3.3 -13.585) (end 3.3 -13.585) (layer F.Fab) (width 0.1))
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(fp_line (start 3.3 -13.585) (end 3.3 13.585) (layer F.Fab) (width 0.1))
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(fp_line (start 3.3 13.585) (end -3.3 13.585) (layer F.Fab) (width 0.1))
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(fp_line (start -3.3 13.585) (end -3.3 -13.585) (layer F.Fab) (width 0.1))
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(fp_line (start -3.3 -12.315) (end -2.03 -13.585) (layer F.Fab) (width 0.1))
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(fp_line (start -4.385 -13.585) (end 3.3 -13.585) (layer F.SilkS) (width 0.2))
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(fp_line (start -3.3 13.585) (end 3.3 13.585) (layer F.SilkS) (width 0.2))
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(pad 1 thru_hole rect (at -3.81 -11.43) (size 1.15 1.15) (drill 0.75) (layers *.Cu *.Mask))
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(pad 2 thru_hole circle (at -3.81 -8.89) (size 1.15 1.15) (drill 0.75) (layers *.Cu *.Mask))
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(pad 3 thru_hole circle (at -3.81 -6.35) (size 1.15 1.15) (drill 0.75) (layers *.Cu *.Mask))
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(pad 4 thru_hole circle (at -3.81 -3.81) (size 1.15 1.15) (drill 0.75) (layers *.Cu *.Mask))
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(pad 5 thru_hole circle (at -3.81 -1.27) (size 1.15 1.15) (drill 0.75) (layers *.Cu *.Mask))
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(pad 6 thru_hole circle (at -3.81 1.27) (size 1.15 1.15) (drill 0.75) (layers *.Cu *.Mask))
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(pad 7 thru_hole circle (at -3.81 3.81) (size 1.15 1.15) (drill 0.75) (layers *.Cu *.Mask))
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(pad 8 thru_hole circle (at -3.81 6.35) (size 1.15 1.15) (drill 0.75) (layers *.Cu *.Mask))
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(pad 9 thru_hole circle (at -3.81 8.89) (size 1.15 1.15) (drill 0.75) (layers *.Cu *.Mask))
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(pad 10 thru_hole circle (at -3.81 11.43) (size 1.15 1.15) (drill 0.75) (layers *.Cu *.Mask))
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(pad 11 thru_hole circle (at 3.81 11.43) (size 1.15 1.15) (drill 0.75) (layers *.Cu *.Mask))
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(pad 12 thru_hole circle (at 3.81 8.89) (size 1.15 1.15) (drill 0.75) (layers *.Cu *.Mask))
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(pad 13 thru_hole circle (at 3.81 6.35) (size 1.15 1.15) (drill 0.75) (layers *.Cu *.Mask))
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(pad 14 thru_hole circle (at 3.81 3.81) (size 1.15 1.15) (drill 0.75) (layers *.Cu *.Mask))
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(pad 15 thru_hole circle (at 3.81 1.27) (size 1.15 1.15) (drill 0.75) (layers *.Cu *.Mask))
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(pad 16 thru_hole circle (at 3.81 -1.27) (size 1.15 1.15) (drill 0.75) (layers *.Cu *.Mask))
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(pad 17 thru_hole circle (at 3.81 -3.81) (size 1.15 1.15) (drill 0.75) (layers *.Cu *.Mask))
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(pad 18 thru_hole circle (at 3.81 -6.35) (size 1.15 1.15) (drill 0.75) (layers *.Cu *.Mask))
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(pad 19 thru_hole circle (at 3.81 -8.89) (size 1.15 1.15) (drill 0.75) (layers *.Cu *.Mask))
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(pad 20 thru_hole circle (at 3.81 -11.43) (size 1.15 1.15) (drill 0.75) (layers *.Cu *.Mask))
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(model SN74LS273NE4.stp
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(at (xyz 0 0 0))
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(scale (xyz 1 1 1))
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(rotate (xyz 0 0 0))
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)
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)
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9
circuit/SN74LS273NE4/KiCad/SN74LS273NE4.dcm
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9
circuit/SN74LS273NE4/KiCad/SN74LS273NE4.dcm
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EESchema-DOCLIB Version 2.0
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#
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$CMP SN74LS273NE4
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D Flip Flops Octal D-Type Flip-Flop w/Clear
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K
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F http://www.ti.com/lit/ds/sdls090/sdls090.pdf
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$ENDCMP
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#
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#End Doc Library
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41
circuit/SN74LS273NE4/KiCad/SN74LS273NE4.lib
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41
circuit/SN74LS273NE4/KiCad/SN74LS273NE4.lib
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@@ -0,0 +1,41 @@
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EESchema-LIBRARY Version 2.3
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#encoding utf-8
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#SamacSys ECAD Model SN74LS273NE4
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#/796887/230744/2.46/20/3/Integrated Circuit
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DEF SN74LS273NE4 IC 0 30 Y Y 1 F N
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F0 "IC" 950 300 50 H V L CNN
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F1 "SN74LS273NE4" 950 200 50 H V L CNN
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F2 "DIP762W55P254L2642H457Q20N" 950 100 50 H I L CNN
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F3 "http://www.ti.com/lit/ds/sdls090/sdls090.pdf" 950 0 50 H I L CNN
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F4 "Flip Flops Octal D-Type Flip-Flop w/Clear" 950 -100 50 H I L CNN "Description"
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F5 "4.57" 950 -200 50 H I L CNN "Height"
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F6 "595-SN74LS273NE4" 950 -300 50 H I L CNN "Mouser2 Part Number"
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F7 "https://www.mouser.com/Search/Refine.aspx?Keyword=595-SN74LS273NE4" 950 -400 50 H I L CNN "Mouser2 Price/Stock"
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F8 "Texas Instruments" 950 -500 50 H I L CNN "Manufacturer_Name"
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F9 "SN74LS273NE4" 950 -600 50 H I L CNN "Manufacturer_Part_Number"
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DRAW
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X ~CLR 1 0 0 200 R 50 50 0 0 I
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X 1Q 2 0 -100 200 R 50 50 0 0 O
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X 1D 3 0 -200 200 R 50 50 0 0 I
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X 2D 4 0 -300 200 R 50 50 0 0 I
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X 2Q 5 0 -400 200 R 50 50 0 0 O
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X 3Q 6 0 -500 200 R 50 50 0 0 O
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X 3D 7 0 -600 200 R 50 50 0 0 I
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X 4D 8 0 -700 200 R 50 50 0 0 I
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X 4Q 9 0 -800 200 R 50 50 0 0 O
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X GND 10 0 -900 200 R 50 50 0 0 W
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X VCC 20 1100 0 200 L 50 50 0 0 W
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X 8Q 19 1100 -100 200 L 50 50 0 0 O
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X 8D 18 1100 -200 200 L 50 50 0 0 I
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X 7D 17 1100 -300 200 L 50 50 0 0 I
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X 7Q 16 1100 -400 200 L 50 50 0 0 O
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X 6Q 15 1100 -500 200 L 50 50 0 0 O
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X 6D 14 1100 -600 200 L 50 50 0 0 I
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X 5D 13 1100 -700 200 L 50 50 0 0 I
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X 5Q 12 1100 -800 200 L 50 50 0 0 O
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X CLK 11 1100 -900 200 L 50 50 0 0 I
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P 5 0 1 6 200 100 900 100 900 -1000 200 -1000 200 100 N
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ENDDRAW
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ENDDEF
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#
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#End Library
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170
circuit/SN74LS273NE4/KiCad/SN74LS273NE4.mod
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170
circuit/SN74LS273NE4/KiCad/SN74LS273NE4.mod
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@@ -0,0 +1,170 @@
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PCBNEW-LibModule-V1 2020-04-22 17:25:09
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# encoding utf-8
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Units mm
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$INDEX
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DIP762W55P254L2642H457Q20N
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$EndINDEX
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$MODULE DIP762W55P254L2642H457Q20N
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Po 0 0 0 15 5ea06fe5 00000000 ~~
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Li DIP762W55P254L2642H457Q20N
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Cd CASE 738–03
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Kw Integrated Circuit
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Sc 0
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At STD
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AR
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Op 0 0 0
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T0 0 0 1.27 1.27 0 0.254 N V 21 N "IC**"
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T1 0 0 1.27 1.27 0 0.254 N I 21 N "DIP762W55P254L2642H457Q20N"
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DS -4.635 -13.835 4.635 -13.835 0.05 24
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DS 4.635 -13.835 4.635 13.835 0.05 24
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DS 4.635 13.835 -4.635 13.835 0.05 24
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DS -4.635 13.835 -4.635 -13.835 0.05 24
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DS -3.3 -13.585 3.3 -13.585 0.1 24
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DS 3.3 -13.585 3.3 13.585 0.1 24
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DS 3.3 13.585 -3.3 13.585 0.1 24
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DS -3.3 13.585 -3.3 -13.585 0.1 24
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DS -3.3 -12.315 -2.03 -13.585 0.1 24
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DS -4.385 -13.585 3.3 -13.585 0.2 21
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DS -3.3 13.585 3.3 13.585 0.2 21
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$PAD
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Po -3.81 -11.43
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Sh "1" R 1.15 1.15 0 0 900
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Dr 0.75 0 0
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At STD N 00E0FFFF
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Ne 0 ""
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$EndPAD
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$PAD
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Po -3.81 -8.89
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Sh "2" C 1.15 1.15 0 0 900
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Dr 0.75 0 0
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At STD N 00E0FFFF
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Ne 0 ""
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$EndPAD
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$PAD
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Po -3.81 -6.35
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Sh "3" C 1.15 1.15 0 0 900
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Dr 0.75 0 0
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At STD N 00E0FFFF
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Ne 0 ""
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$EndPAD
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$PAD
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Po -3.81 -3.81
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Sh "4" C 1.15 1.15 0 0 900
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Dr 0.75 0 0
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At STD N 00E0FFFF
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Ne 0 ""
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$EndPAD
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$PAD
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Po -3.81 -1.27
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Sh "5" C 1.15 1.15 0 0 900
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Dr 0.75 0 0
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At STD N 00E0FFFF
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Ne 0 ""
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$EndPAD
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$PAD
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Po -3.81 1.27
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Sh "6" C 1.15 1.15 0 0 900
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Dr 0.75 0 0
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At STD N 00E0FFFF
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Ne 0 ""
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$EndPAD
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$PAD
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Po -3.81 3.81
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Sh "7" C 1.15 1.15 0 0 900
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Dr 0.75 0 0
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At STD N 00E0FFFF
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Ne 0 ""
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$EndPAD
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$PAD
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Po -3.81 6.35
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Sh "8" C 1.15 1.15 0 0 900
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Dr 0.75 0 0
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At STD N 00E0FFFF
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Ne 0 ""
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$EndPAD
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$PAD
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Po -3.81 8.89
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Sh "9" C 1.15 1.15 0 0 900
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Dr 0.75 0 0
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At STD N 00E0FFFF
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Ne 0 ""
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$EndPAD
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$PAD
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Po -3.81 11.43
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Sh "10" C 1.15 1.15 0 0 900
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Dr 0.75 0 0
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At STD N 00E0FFFF
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Ne 0 ""
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$EndPAD
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$PAD
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Po 3.81 11.43
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Sh "11" C 1.15 1.15 0 0 900
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Dr 0.75 0 0
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At STD N 00E0FFFF
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Ne 0 ""
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$EndPAD
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$PAD
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Po 3.81 8.89
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Sh "12" C 1.15 1.15 0 0 900
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Dr 0.75 0 0
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At STD N 00E0FFFF
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Ne 0 ""
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$EndPAD
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$PAD
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Po 3.81 6.35
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Sh "13" C 1.15 1.15 0 0 900
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Dr 0.75 0 0
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At STD N 00E0FFFF
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Ne 0 ""
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$EndPAD
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$PAD
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Po 3.81 3.81
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Sh "14" C 1.15 1.15 0 0 900
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Dr 0.75 0 0
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At STD N 00E0FFFF
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Ne 0 ""
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$EndPAD
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$PAD
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Po 3.81 1.27
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Sh "15" C 1.15 1.15 0 0 900
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Dr 0.75 0 0
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At STD N 00E0FFFF
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Ne 0 ""
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$EndPAD
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$PAD
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Po 3.81 -1.27
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Sh "16" C 1.15 1.15 0 0 900
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Dr 0.75 0 0
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At STD N 00E0FFFF
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Ne 0 ""
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$EndPAD
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$PAD
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Po 3.81 -3.81
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Sh "17" C 1.15 1.15 0 0 900
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Dr 0.75 0 0
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At STD N 00E0FFFF
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Ne 0 ""
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$EndPAD
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$PAD
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Po 3.81 -6.35
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Sh "18" C 1.15 1.15 0 0 900
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Dr 0.75 0 0
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At STD N 00E0FFFF
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Ne 0 ""
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$EndPAD
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$PAD
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Po 3.81 -8.89
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Sh "19" C 1.15 1.15 0 0 900
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Dr 0.75 0 0
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At STD N 00E0FFFF
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Ne 0 ""
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$EndPAD
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$PAD
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Po 3.81 -11.43
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Sh "20" C 1.15 1.15 0 0 900
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Dr 0.75 0 0
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At STD N 00E0FFFF
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Ne 0 ""
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$EndPAD
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$EndMODULE DIP762W55P254L2642H457Q20N
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$EndLIBRARY
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BIN
circuit/SN74LS273NE4/KiCad/SN74LS273NE4.zip
Normal file
BIN
circuit/SN74LS273NE4/KiCad/SN74LS273NE4.zip
Normal file
Binary file not shown.
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